CSRNG Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	32.932us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	22.801us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	81.914us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	4.000s	31.691us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	44.558us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	21.555us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	81.914us	20	20	100.00
		csrng_csr_aliasing	4.000s	44.558us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	5.000s	12.533us	200	200	100.00
V2	alerts	csrng_alert	5.000s	12.031us	500	500	100.00
V2	err	csrng_err	9.000s	21.628us	500	500	100.00
V2	cmds	csrng_cmds	5.000s	23.990us	50	50	100.00
V2	life cycle	csrng_cmds	5.000s	23.990us	50	50	100.00
V2	stress_all	csrng_stress_all	5.000s	18.330us	50	50	100.00
V2	intr_test	csrng_intr_test	4.000s	26.748us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	172.652us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	4.000s	10.942us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	4.000s	10.942us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	22.801us	5	5	100.00
		csrng_csr_rw	5.000s	81.914us	20	20	100.00
		csrng_csr_aliasing	4.000s	44.558us	5	5	100.00
		csrng_same_csr_outstanding	4.000s	26.524us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	22.801us	5	5	100.00
		csrng_csr_rw	5.000s	81.914us	20	20	100.00
		csrng_csr_aliasing	4.000s	44.558us	5	5	100.00
		csrng_same_csr_outstanding	4.000s	26.524us	20	20	100.00
V2		TOTAL			1440	1440	100.00
V2S	tl_intg_err	csrng_sec_cm	5.000s	24.761us	5	5	100.00
		csrng_tl_intg_err	4.000s	13.654us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	12.219us	50	50	100.00
		csrng_csr_rw	5.000s	81.914us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	5.000s	12.031us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	5.000s	18.330us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	5.000s	12.031us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	5.000s	18.330us	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	5.000s	12.031us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	4.000s	13.654us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
		csrng_sec_cm	5.000s	24.761us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	5.000s	12.533us	200	200	100.00
		csrng_err	9.000s	21.628us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	5.000s	32.577us	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1630	1630	100.00

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test csrng has 1 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_merge/merged/cov_merge.log

        [Executing]:
        make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
      
        [make]: cov_merge
        imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
        *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
        Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
        Created log file /nightly/current_run/opentitan/startup.log
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test csrng has 1 failures.
    • cov_report
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.log