DMA Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 dma_memory_smoke dma_memory_smoke 35.000s 22.196us 25 25 100.00
V1 dma_handshake_smoke dma_handshake_smoke 35.000s 11.550us 25 25 100.00
V1 dma_generic_smoke dma_generic_smoke 35.000s 18.045us 50 50 100.00
V1 csr_hw_reset dma_csr_hw_reset 3.000s 72.500us 5 5 100.00
V1 csr_rw dma_csr_rw 3.000s 39.400us 20 20 100.00
V1 csr_bit_bash dma_csr_bit_bash 8.000s 45.621us 5 5 100.00
V1 csr_aliasing dma_csr_aliasing 3.000s 11.602us 5 5 100.00
V1 csr_mem_rw_with_rand_reset dma_csr_mem_rw_with_rand_reset 3.000s 21.233us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr dma_csr_rw 3.000s 39.400us 20 20 100.00
dma_csr_aliasing 3.000s 11.602us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 dma_memory_region_lock dma_memory_region_lock 35.000s 30.632us 5 5 100.00
V2 dma_memory_tl_error dma_memory_stress 35.000s 13.244us 3 3 100.00
V2 dma_handshake_tl_error dma_handshake_stress 35.000s 34.514us 3 3 100.00
V2 dma_handshake_stress dma_handshake_stress 35.000s 34.514us 3 3 100.00
V2 dma_memory_stress dma_memory_stress 35.000s 13.244us 3 3 100.00
V2 dma_generic_stress dma_generic_stress 35.000s 12.313us 5 5 100.00
V2 dma_handshake_mem_buffer_overflow dma_handshake_stress 35.000s 34.514us 3 3 100.00
V2 dma_abort dma_abort 35.000s 21.403us 5 5 100.00
V2 dma_stress_all dma_stress_all 35.000s 45.311us 3 3 100.00
V2 alert_test dma_alert_test 35.000s 11.799us 50 50 100.00
V2 intr_test dma_intr_test 4.000s 11.360us 50 50 100.00
V2 tl_d_oob_addr_access dma_tl_errors 3.000s 55.599us 20 20 100.00
V2 tl_d_illegal_access dma_tl_errors 3.000s 55.599us 20 20 100.00
V2 tl_d_outstanding_access dma_csr_hw_reset 3.000s 72.500us 5 5 100.00
dma_csr_rw 3.000s 39.400us 20 20 100.00
dma_csr_aliasing 3.000s 11.602us 5 5 100.00
dma_same_csr_outstanding 4.000s 11.998us 20 20 100.00
V2 tl_d_partial_access dma_csr_hw_reset 3.000s 72.500us 5 5 100.00
dma_csr_rw 3.000s 39.400us 20 20 100.00
dma_csr_aliasing 3.000s 11.602us 5 5 100.00
dma_same_csr_outstanding 4.000s 11.998us 20 20 100.00
V2 TOTAL 164 164 100.00
V2S dma_illegal_addr_range dma_mem_enabled 35.000s 10.055us 5 5 100.00
dma_generic_stress 35.000s 12.313us 5 5 100.00
dma_handshake_stress 35.000s 34.514us 3 3 100.00
V2S dma_config_lock dma_config_lock 35.000s 10.449us 15 15 100.00
V2S tl_intg_err dma_tl_intg_err 4.000s 13.951us 20 20 100.00
dma_sec_cm 35.000s 35.212us 5 5 100.00
V2S TOTAL 45 45 100.00
Unmapped tests dma_short_transfer 35.000s 14.179us 25 25 100.00
dma_longer_transfer 35.000s 22.848us 5 5 100.00
dma_stress_all_with_rand_reset 35.000s 24.026us 1 1 100.00
TOTAL 395 395 100.00

Failure Buckets