EDN Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.340s	12.915us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.740s	12.583us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.760s	12.824us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	0.720s	61.252us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	0.740s	21.977us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.730s	12.423us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.760s	12.824us	20	20	100.00
		edn_csr_aliasing	0.740s	21.977us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.270s	14.357us	300	300	100.00
V2	csrng_commands	edn_genbits	1.270s	14.357us	300	300	100.00
V2	genbits	edn_genbits	1.270s	14.357us	300	300	100.00
V2	interrupts	edn_intr	1.290s	34.690us	50	50	100.00
V2	alerts	edn_alert	1.280s	20.442us	200	200	100.00
V2	errs	edn_err	1.320s	42.095us	100	100	100.00
V2	disable	edn_disable	1.350s	13.631us	50	50	100.00
		edn_disable_auto_req_mode	1.290s	13.695us	50	50	100.00
V2	stress_all	edn_stress_all	1.260s	21.709us	50	50	100.00
V2	intr_test	edn_intr_test	0.770s	13.848us	50	50	100.00
V2	alert_test	edn_alert_test	1.260s	64.295us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	0.730s	38.273us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	0.730s	38.273us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.740s	12.583us	5	5	100.00
		edn_csr_rw	0.760s	12.824us	20	20	100.00
		edn_csr_aliasing	0.740s	21.977us	5	5	100.00
		edn_same_csr_outstanding	0.770s	12.427us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.740s	12.583us	5	5	100.00
		edn_csr_rw	0.760s	12.824us	20	20	100.00
		edn_csr_aliasing	0.740s	21.977us	5	5	100.00
		edn_same_csr_outstanding	0.770s	12.427us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	1.360s	14.047us	5	5	100.00
		edn_tl_intg_err	0.760s	20.705us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.350s	12.230us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.280s	20.442us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	1.360s	14.047us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	1.360s	14.047us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	1.360s	14.047us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	1.360s	14.047us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.280s	20.442us	200	200	100.00
		edn_sec_cm	1.360s	14.047us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.280s	20.442us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	0.760s	20.705us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.310s	13.956us	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1130	1130	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
46.97	80.03	47.36	38.52	0.00	51.17	78.89	32.82