HMAC Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	0.620s	7.342us	0	10	0.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.540s	2.848us	0	5	0.00
V1	csr_rw	hmac_csr_rw	0.590s	2.170us	0	20	0.00
V1	csr_bit_bash	hmac_csr_bit_bash	0.540s	3.586us	0	5	0.00
V1	csr_aliasing	hmac_csr_aliasing	0.530s	5.554us	0	5	0.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	0.580s	1.198us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.590s	2.170us	0	20	0.00
		hmac_csr_aliasing	0.530s	5.554us	0	5	0.00
V1		TOTAL			0	65	0.00
V2	long_msg	hmac_long_msg	0.590s	2.250us	0	10	0.00
V2	back_pressure	hmac_back_pressure	0.590s	1.123us	0	25	0.00
V2	test_vectors	hmac_test_sha256_vectors	1.430s	913.994ns	0	30	0.00
		hmac_test_sha384_vectors	1.400s	2.320us	0	75	0.00
		hmac_test_sha512_vectors	1.440s	1.201us	0	75	0.00
		hmac_test_hmac256_vectors	1.410s	1.459us	0	50	0.00
		hmac_test_hmac384_vectors	1.530s	2.474us	0	60	0.00
		hmac_test_hmac512_vectors	1.440s	2.447us	0	75	0.00
V2	burst_wr	hmac_burst_wr	0.590s	1.401us	0	50	0.00
V2	datapath_stress	hmac_datapath_stress	0.580s	872.806ns	0	10	0.00
V2	error	hmac_error	0.590s	11.620us	0	10	0.00
V2	wipe_secret	hmac_wipe_secret	0.580s	1.398us	0	10	0.00
V2	save_and_restore	hmac_smoke	0.620s	7.342us	0	10	0.00
		hmac_long_msg	0.590s	2.250us	0	10	0.00
		hmac_back_pressure	0.590s	1.123us	0	25	0.00
		hmac_datapath_stress	0.580s	872.806ns	0	10	0.00
		hmac_burst_wr	0.590s	1.401us	0	50	0.00
		hmac_stress_all	0.640s	2.607us	0	50	0.00
V2	fifo_empty_status_interrupt	hmac_smoke	0.620s	7.342us	0	10	0.00
		hmac_long_msg	0.590s	2.250us	0	10	0.00
		hmac_back_pressure	0.590s	1.123us	0	25	0.00
		hmac_datapath_stress	0.580s	872.806ns	0	10	0.00
		hmac_wipe_secret	0.580s	1.398us	0	10	0.00
		hmac_test_sha256_vectors	1.430s	913.994ns	0	30	0.00
		hmac_test_sha384_vectors	1.400s	2.320us	0	75	0.00
		hmac_test_sha512_vectors	1.440s	1.201us	0	75	0.00
		hmac_test_hmac256_vectors	1.410s	1.459us	0	50	0.00
		hmac_test_hmac384_vectors	1.530s	2.474us	0	60	0.00
		hmac_test_hmac512_vectors	1.440s	2.447us	0	75	0.00
V2	wide_digest_configurable_key_length	hmac_smoke	0.620s	7.342us	0	10	0.00
		hmac_long_msg	0.590s	2.250us	0	10	0.00
		hmac_back_pressure	0.590s	1.123us	0	25	0.00
		hmac_datapath_stress	0.580s	872.806ns	0	10	0.00
		hmac_burst_wr	0.590s	1.401us	0	50	0.00
		hmac_error	0.590s	11.620us	0	10	0.00
		hmac_wipe_secret	0.580s	1.398us	0	10	0.00
		hmac_test_sha256_vectors	1.430s	913.994ns	0	30	0.00
		hmac_test_sha384_vectors	1.400s	2.320us	0	75	0.00
		hmac_test_sha512_vectors	1.440s	1.201us	0	75	0.00
		hmac_test_hmac256_vectors	1.410s	1.459us	0	50	0.00
		hmac_test_hmac384_vectors	1.530s	2.474us	0	60	0.00
		hmac_test_hmac512_vectors	1.440s	2.447us	0	75	0.00
		hmac_stress_all	0.640s	2.607us	0	50	0.00
V2	stress_all	hmac_stress_all	0.640s	2.607us	0	50	0.00
V2	alert_test	hmac_alert_test	0.630s	2.582us	0	50	0.00
V2	intr_test	hmac_intr_test	0.600s	1.530us	0	50	0.00
V2	tl_d_oob_addr_access	hmac_tl_errors	0.570s	1.113us	0	20	0.00
V2	tl_d_illegal_access	hmac_tl_errors	0.570s	1.113us	0	20	0.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.540s	2.848us	0	5	0.00
		hmac_csr_rw	0.590s	2.170us	0	20	0.00
		hmac_csr_aliasing	0.530s	5.554us	0	5	0.00
		hmac_same_csr_outstanding	0.570s	902.818ns	0	20	0.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.540s	2.848us	0	5	0.00
		hmac_csr_rw	0.590s	2.170us	0	20	0.00
		hmac_csr_aliasing	0.530s	5.554us	0	5	0.00
		hmac_same_csr_outstanding	0.570s	902.818ns	0	20	0.00
V2		TOTAL			0	670	0.00
V2S	tl_intg_err	hmac_sec_cm	0.570s	2.000us	0	5	0.00
		hmac_tl_intg_err	0.590s	2.617us	0	20	0.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	0.590s	2.617us	0	20	0.00
V2S		TOTAL			0	25	0.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	0.620s	7.342us	0	10	0.00
V3	stress_reset	hmac_stress_reset	0.610s	1.195us	0	25	0.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	0.600s	3.952us	0	35	0.00
V3		TOTAL			0	60	0.00
	Unmapped tests	hmac_directed	0.500s	1.278us	0	1	0.00
		TOTAL			0	821	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class! has 821 failures:
  • Test hmac_smoke has 10 failures.

    • 0.hmac_smoke.72687787778351057959591863692996779799763910289262863428193384093576563171432
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_smoke/latest/run.log

        UVM_FATAL @   1352708 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1352708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.hmac_smoke.51624150522986509915934878857147050319598873969447023426409353726970661185412
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/1.hmac_smoke/latest/run.log

        UVM_FATAL @   1683195 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1683195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

  • Test hmac_long_msg has 10 failures.

    • 0.hmac_long_msg.47001436263332525761009352057560037342858236579969874026291777676305041045922
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_long_msg/latest/run.log

        UVM_FATAL @   1616798 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1616798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.hmac_long_msg.74496387584037098858544326581231095942247076160436213192140984416962868686904
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/1.hmac_long_msg/latest/run.log

        UVM_FATAL @   1282402 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1282402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

  • Test hmac_stress_reset has 25 failures.

    • 0.hmac_stress_reset.42841939080341862324438123485126491495998988617737884533055317712955365888888
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_stress_reset/latest/run.log

        UVM_FATAL @   3165080 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3165080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.hmac_stress_reset.55373342664281093995553462242862667618192538285045248080010446875920657744573
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/1.hmac_stress_reset/latest/run.log

        UVM_FATAL @   6941199 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   6941199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 23 more failures.

  • Test hmac_back_pressure has 25 failures.

    • 0.hmac_back_pressure.24475702756744710671556107693040993662592592501511356862569978747349732683738
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_back_pressure/latest/run.log

        UVM_FATAL @   3190384 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3190384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.hmac_back_pressure.95760751221886093725066144795878069048702987874074162208623013140329053811327
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/1.hmac_back_pressure/latest/run.log

        UVM_FATAL @   1214841 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1214841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 23 more failures.

  • Test hmac_datapath_stress has 10 failures.

    • 0.hmac_datapath_stress.29457707125399283267943767814077465333276734625998047479496242553559671533953
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_datapath_stress/latest/run.log

        UVM_FATAL @    819830 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    819830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.hmac_datapath_stress.46954100081764585029520925095979817156639976547125622584515286431725673680909
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/1.hmac_datapath_stress/latest/run.log

        UVM_FATAL @   1279589 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1279589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

  • ... and 23 more tests.
• Job killed most likely because its dependent job failed. has 2 failures:
  • Test hmac has 2 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/cov_merge/merged.vdb/cov_merge.log

    • cov_report
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/cov_report/cov_report.log