I2C Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 1.320s 1.639us 0 50 0.00
V1 target_smoke i2c_target_smoke 1.320s 2.410us 0 50 0.00
V1 csr_hw_reset i2c_csr_hw_reset 1.110s 875.847ns 0 5 0.00
V1 csr_rw i2c_csr_rw 1.080s 960.319ns 0 20 0.00
V1 csr_bit_bash i2c_csr_bit_bash 1.040s 11.179us 0 5 0.00
V1 csr_aliasing i2c_csr_aliasing 1.080s 885.870ns 0 5 0.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 1.110s 937.445ns 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 1.080s 960.319ns 0 20 0.00
i2c_csr_aliasing 1.080s 885.870ns 0 5 0.00
V1 TOTAL 0 155 0.00
V2 host_error_intr i2c_host_error_intr 1.330s 879.734ns 0 50 0.00
V2 host_stress_all i2c_host_stress_all 1.290s 4.349us 0 50 0.00
V2 host_maxperf i2c_host_perf 1.360s 1.366us 0 50 0.00
V2 host_override i2c_host_override 1.330s 1.920us 0 50 0.00
V2 host_fifo_watermark i2c_host_fifo_watermark 1.300s 4.803us 0 50 0.00
V2 host_fifo_overflow i2c_host_fifo_overflow 1.390s 1.801us 0 50 0.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 1.330s 1.086us 0 50 0.00
i2c_host_fifo_fmt_empty 1.320s 4.963us 0 50 0.00
i2c_host_fifo_reset_rx 1.320s 1.154us 0 50 0.00
V2 host_fifo_full i2c_host_fifo_full 1.330s 4.031us 0 50 0.00
V2 host_timeout i2c_host_stretch_timeout 1.390s 817.939ns 0 50 0.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 1.360s 2.974us 0 50 0.00
V2 target_glitch i2c_target_glitch 0.590s 4.872us 0 2 0.00
V2 target_stress_all i2c_target_stress_all 1.310s 868.096ns 0 50 0.00
V2 target_maxperf i2c_target_perf 1.360s 775.159ns 0 50 0.00
V2 target_fifo_empty i2c_target_stress_rd 1.300s 3.278us 0 50 0.00
i2c_target_intr_smoke 1.350s 4.755us 0 50 0.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 1.330s 3.009us 0 50 0.00
i2c_target_fifo_reset_tx 1.360s 699.319ns 0 50 0.00
V2 target_fifo_full i2c_target_stress_wr 1.330s 1.798us 0 50 0.00
i2c_target_stress_rd 1.300s 3.278us 0 50 0.00
i2c_target_intr_stress_wr 1.300s 1.151us 0 50 0.00
V2 target_timeout i2c_target_timeout 1.270s 1.097us 0 50 0.00
V2 target_clock_stretch i2c_target_stretch 1.270s 711.238ns 0 50 0.00
V2 bad_address i2c_target_bad_addr 1.370s 4.439us 0 50 0.00
V2 target_mode_glitch i2c_target_hrst 1.340s 687.405ns 0 50 0.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 1.350s 5.757us 0 50 0.00
i2c_target_fifo_watermarks_tx 1.310s 3.980us 0 50 0.00
V2 host_mode_config_perf i2c_host_perf 1.360s 1.366us 0 50 0.00
i2c_host_perf_precise 1.300s 1.025us 0 50 0.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 1.390s 817.939ns 0 50 0.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 1.320s 4.080us 0 50 0.00
V2 target_mode_nack_generation i2c_target_nack_acqfull 1.310s 1.167us 0 50 0.00
i2c_target_nack_acqfull_addr 1.300s 1.160us 0 50 0.00
i2c_target_nack_txstretch 1.320s 1.047us 0 50 0.00
V2 host_mode_halt_on_nak i2c_host_may_nack 1.330s 1.134us 0 50 0.00
V2 target_mode_smbus_maxlen i2c_target_smbus_maxlen 1.320s 3.856us 0 50 0.00
V2 alert_test i2c_alert_test 1.270s 6.038us 0 50 0.00
V2 intr_test i2c_intr_test 1.090s 2.948us 0 50 0.00
V2 tl_d_oob_addr_access i2c_tl_errors 1.070s 4.644us 0 20 0.00
V2 tl_d_illegal_access i2c_tl_errors 1.070s 4.644us 0 20 0.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 1.110s 875.847ns 0 5 0.00
i2c_csr_rw 1.080s 960.319ns 0 20 0.00
i2c_csr_aliasing 1.080s 885.870ns 0 5 0.00
i2c_same_csr_outstanding 1.110s 2.605us 0 20 0.00
V2 tl_d_partial_access i2c_csr_hw_reset 1.110s 875.847ns 0 5 0.00
i2c_csr_rw 1.080s 960.319ns 0 20 0.00
i2c_csr_aliasing 1.080s 885.870ns 0 5 0.00
i2c_same_csr_outstanding 1.110s 2.605us 0 20 0.00
V2 TOTAL 0 1792 0.00
V2S tl_intg_err i2c_tl_intg_err 1.050s 6.814us 0 20 0.00
i2c_sec_cm 0.580s 4.139us 0 5 0.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 1.050s 6.814us 0 20 0.00
V2S TOTAL 0 25 0.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 0.590s 750.589ns 0 10 0.00
V3 target_error_intr i2c_target_unexp_stop 1.280s 2.338us 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 0.590s 897.596ns 0 10 0.00
V3 TOTAL 0 70 0.00
TOTAL 0 2042 0.00

Failure Buckets