KEYMGR Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.450s 234.044us 0 50 0.00
V1 random keymgr_random 1.180s 26.142us 0 50 0.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.660s 1.899us 0 5 0.00
V1 csr_rw keymgr_csr_rw 0.690s 2.087us 0 20 0.00
V1 csr_bit_bash keymgr_csr_bit_bash 0.670s 4.046us 0 5 0.00
V1 csr_aliasing keymgr_csr_aliasing 0.650s 1.862us 0 5 0.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 0.690s 1.379us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.690s 2.087us 0 20 0.00
keymgr_csr_aliasing 0.650s 1.862us 0 5 0.00
V1 TOTAL 0 155 0.00
V2 cfgen_during_op keymgr_cfg_regwen 1.220s 30.216us 0 50 0.00
V2 sideload keymgr_sideload 1.270s 74.117us 0 50 0.00
keymgr_sideload_kmac 1.110s 2.991us 0 50 0.00
keymgr_sideload_aes 1.120s 4.165us 0 50 0.00
keymgr_sideload_otbn 1.340s 72.254us 0 50 0.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.260s 44.416us 0 50 0.00
V2 lc_disable keymgr_lc_disable 1.120s 9.510us 0 50 0.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.180s 54.131us 0 50 0.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.500s 22.605us 0 50 0.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.290s 36.638us 0 50 0.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.060s 43.989us 0 50 0.00
V2 stress_all keymgr_stress_all 1.070s 21.344us 0 50 0.00
V2 intr_test keymgr_intr_test 1.400s 24.232us 0 50 0.00
V2 alert_test keymgr_alert_test 1.120s 3.011us 0 50 0.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.190s 140.854us 0 20 0.00
V2 tl_d_illegal_access keymgr_tl_errors 1.190s 140.854us 0 20 0.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.660s 1.899us 0 5 0.00
keymgr_csr_rw 0.690s 2.087us 0 20 0.00
keymgr_csr_aliasing 0.650s 1.862us 0 5 0.00
keymgr_same_csr_outstanding 0.690s 6.994us 0 20 0.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.660s 1.899us 0 5 0.00
keymgr_csr_rw 0.690s 2.087us 0 20 0.00
keymgr_csr_aliasing 0.650s 1.862us 0 5 0.00
keymgr_same_csr_outstanding 0.690s 6.994us 0 20 0.00
V2 TOTAL 0 740 0.00
V2S sec_cm_additional_check keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S tl_intg_err keymgr_sec_cm 0.890s 1.990us 0 5 0.00
keymgr_tl_intg_err 0.660s 2.770us 0 20 0.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 0.740s 10.423us 0 20 0.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 0.740s 10.423us 0 20 0.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 0.740s 10.423us 0 20 0.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 0.740s 10.423us 0 20 0.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 0.660s 4.749us 0 20 0.00
V2S prim_count_check keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S prim_fsm_check keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 0.660s 2.770us 0 20 0.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 0.740s 10.423us 0 20 0.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.220s 30.216us 0 50 0.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.180s 26.142us 0 50 0.00
keymgr_csr_rw 0.690s 2.087us 0 20 0.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.180s 26.142us 0 50 0.00
keymgr_csr_rw 0.690s 2.087us 0 20 0.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.180s 26.142us 0 50 0.00
keymgr_csr_rw 0.690s 2.087us 0 20 0.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 1.120s 9.510us 0 50 0.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.290s 36.638us 0 50 0.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.290s 36.638us 0 50 0.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.180s 26.142us 0 50 0.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.100s 16.040us 0 50 0.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.380s 38.478us 0 50 0.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 1.120s 9.510us 0 50 0.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.380s 38.478us 0 50 0.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.380s 38.478us 0 50 0.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.380s 38.478us 0 50 0.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 0.890s 1.990us 0 5 0.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.380s 38.478us 0 50 0.00
V2S TOTAL 0 165 0.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 1.140s 30.251us 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 0 1110 0.00

Failure Buckets