751b8fb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 1.450s | 234.044us | 0 | 50 | 0.00 |
| V1 | random | keymgr_random | 1.180s | 26.142us | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 0.660s | 1.899us | 0 | 5 | 0.00 |
| V1 | csr_rw | keymgr_csr_rw | 0.690s | 2.087us | 0 | 20 | 0.00 |
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 0.670s | 4.046us | 0 | 5 | 0.00 |
| V1 | csr_aliasing | keymgr_csr_aliasing | 0.650s | 1.862us | 0 | 5 | 0.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 0.690s | 1.379us | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 0.690s | 2.087us | 0 | 20 | 0.00 |
| keymgr_csr_aliasing | 0.650s | 1.862us | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 155 | 0.00 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 1.220s | 30.216us | 0 | 50 | 0.00 |
| V2 | sideload | keymgr_sideload | 1.270s | 74.117us | 0 | 50 | 0.00 |
| keymgr_sideload_kmac | 1.110s | 2.991us | 0 | 50 | 0.00 | ||
| keymgr_sideload_aes | 1.120s | 4.165us | 0 | 50 | 0.00 | ||
| keymgr_sideload_otbn | 1.340s | 72.254us | 0 | 50 | 0.00 | ||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 1.260s | 44.416us | 0 | 50 | 0.00 |
| V2 | lc_disable | keymgr_lc_disable | 1.120s | 9.510us | 0 | 50 | 0.00 |
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 1.180s | 54.131us | 0 | 50 | 0.00 |
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.500s | 22.605us | 0 | 50 | 0.00 |
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.290s | 36.638us | 0 | 50 | 0.00 |
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 1.060s | 43.989us | 0 | 50 | 0.00 |
| V2 | stress_all | keymgr_stress_all | 1.070s | 21.344us | 0 | 50 | 0.00 |
| V2 | intr_test | keymgr_intr_test | 1.400s | 24.232us | 0 | 50 | 0.00 |
| V2 | alert_test | keymgr_alert_test | 1.120s | 3.011us | 0 | 50 | 0.00 |
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 1.190s | 140.854us | 0 | 20 | 0.00 |
| V2 | tl_d_illegal_access | keymgr_tl_errors | 1.190s | 140.854us | 0 | 20 | 0.00 |
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 0.660s | 1.899us | 0 | 5 | 0.00 |
| keymgr_csr_rw | 0.690s | 2.087us | 0 | 20 | 0.00 | ||
| keymgr_csr_aliasing | 0.650s | 1.862us | 0 | 5 | 0.00 | ||
| keymgr_same_csr_outstanding | 0.690s | 6.994us | 0 | 20 | 0.00 | ||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 0.660s | 1.899us | 0 | 5 | 0.00 |
| keymgr_csr_rw | 0.690s | 2.087us | 0 | 20 | 0.00 | ||
| keymgr_csr_aliasing | 0.650s | 1.862us | 0 | 5 | 0.00 | ||
| keymgr_same_csr_outstanding | 0.690s | 6.994us | 0 | 20 | 0.00 | ||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | tl_intg_err | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| keymgr_tl_intg_err | 0.660s | 2.770us | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 0.740s | 10.423us | 0 | 20 | 0.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 0.740s | 10.423us | 0 | 20 | 0.00 |
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 0.740s | 10.423us | 0 | 20 | 0.00 |
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 0.740s | 10.423us | 0 | 20 | 0.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 0.660s | 4.749us | 0 | 20 | 0.00 |
| V2S | prim_count_check | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | prim_fsm_check | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 0.660s | 2.770us | 0 | 20 | 0.00 |
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 0.740s | 10.423us | 0 | 20 | 0.00 |
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.220s | 30.216us | 0 | 50 | 0.00 |
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.180s | 26.142us | 0 | 50 | 0.00 |
| keymgr_csr_rw | 0.690s | 2.087us | 0 | 20 | 0.00 | ||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.180s | 26.142us | 0 | 50 | 0.00 |
| keymgr_csr_rw | 0.690s | 2.087us | 0 | 20 | 0.00 | ||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.180s | 26.142us | 0 | 50 | 0.00 |
| keymgr_csr_rw | 0.690s | 2.087us | 0 | 20 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 1.120s | 9.510us | 0 | 50 | 0.00 |
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.290s | 36.638us | 0 | 50 | 0.00 |
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.290s | 36.638us | 0 | 50 | 0.00 |
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.180s | 26.142us | 0 | 50 | 0.00 |
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 1.100s | 16.040us | 0 | 50 | 0.00 |
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 1.380s | 38.478us | 0 | 50 | 0.00 |
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 1.120s | 9.510us | 0 | 50 | 0.00 |
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 1.380s | 38.478us | 0 | 50 | 0.00 |
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 1.380s | 38.478us | 0 | 50 | 0.00 |
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 1.380s | 38.478us | 0 | 50 | 0.00 |
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 0.890s | 1.990us | 0 | 5 | 0.00 |
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 1.380s | 38.478us | 0 | 50 | 0.00 |
| V2S | TOTAL | 0 | 165 | 0.00 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 1.140s | 30.251us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1110 | 0.00 |
UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class! has 1004 failures:
0.keymgr_smoke.98183150510565524673234693883913355163319139236860338064006547981045842979108
Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_smoke/latest/run.log
UVM_FATAL @ 9589548 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 9589548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_smoke.76349825684109526062367711106921827007353298267885289135887263731246482575338
Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_smoke/latest/run.log
UVM_FATAL @ 1492139 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 1492139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
0.keymgr_sideload.51317895456288598239290541221000502018956196505650350899706024401523578227073
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload/latest/run.log
UVM_FATAL @ 975012 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 975012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_sideload.111933766862862877806543655310267745712241894380785507924384903711827574893733
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_sideload/latest/run.log
UVM_FATAL @ 5691498 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 5691498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.keymgr_sideload_kmac.12197475567562757079722231109643467832144172290767637832186234442412050152416
Line 81, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest/run.log
UVM_FATAL @ 9680243 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 9680243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_sideload_kmac.6739458720972304475817144500204952550649455215680867741078197115370444712418
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest/run.log
UVM_FATAL @ 21541813 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 21541813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.keymgr_sideload_aes.71859209470174138532356697924803496113681049741499500200816854781421819100123
Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_aes/latest/run.log
UVM_FATAL @ 3951782 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 3951782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_sideload_aes.16498557990465017930343940593883189473483224001389568637600888169044919244889
Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_sideload_aes/latest/run.log
UVM_FATAL @ 1664881 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 1664881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.keymgr_sideload_otbn.87408016530434105748245129300746913358777268694292319450970534347772258019909
Line 126, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest/run.log
UVM_FATAL @ 4894540 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 4894540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_sideload_otbn.77149772634707224139701958246090076473081795350549782562740393172157940725290
Line 106, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest/run.log
UVM_FATAL @ 19209754 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 19209754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (keymgr_base_vseq.sv:199) [keymgr_base_vseq] Check failed gmv(ral.op_status.status) == exp_status (* [] vs * [])` has 102 failures:
0.keymgr_shadow_reg_errors.112665051426460485706938399073198629293019531650452639533463809571999612322843
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest/run.log
UVM_ERROR @ 2858696 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 2858696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_shadow_reg_errors.24204360296860368063701808162878688502148551936798003525857764918207425154315
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest/run.log
UVM_ERROR @ 19654324 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 19654324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
0.keymgr_tl_intg_err.8863777364840234084531437009280576118235338845451790305685269660939369011966
Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log
UVM_ERROR @ 4704156 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 4704156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_tl_intg_err.100136453932102246472020849946222041353073845739879538327801009507975676391277
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest/run.log
UVM_ERROR @ 3728280 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 3728280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.keymgr_csr_rw.2223753535051309386350509941796669037024775973332872166782454443202870613762
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log
UVM_ERROR @ 5020468 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 5020468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_csr_rw.62366110348599993477430797568045698575736951879355403980397406429855261664939
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_csr_rw/latest/run.log
UVM_ERROR @ 2979095 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 2979095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.keymgr_csr_bit_bash.35530751368413193052362163339989858627914583439563182223251592169580114837269
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log
UVM_ERROR @ 2519077 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 2519077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_csr_bit_bash.83215544224696805386480109462387004044190271008181549260107612803582151561576
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log
UVM_ERROR @ 4045750 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 4045750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
0.keymgr_csr_aliasing.82664943178611287166672842436601755186502275034813234350706309856494209538809
Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log
UVM_ERROR @ 1861846 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 1861846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_csr_aliasing.93123218954548422074341496018910617495382367730939170682386131079249211427285
Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log
UVM_ERROR @ 5442906 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
UVM_INFO @ 5442906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:
Test keymgr_stress_all has 1 failures.
10.keymgr_stress_all.38629271455296956709131227977370580049974724789118369291121422053518115247521
Line 91, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log
UVM_ERROR @ 7078488 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 7078488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_smoke has 1 failures.
11.keymgr_smoke.85515163351236767507263800717970797816565750903470991831189969491768466797779
Line 121, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_smoke/latest/run.log
UVM_ERROR @ 21608586 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 21608586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_cfg_regwen has 2 failures.
18.keymgr_cfg_regwen.110602453215460179602083368782342390577566915849007905371149316106167413111465
Line 101, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 5356790 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 5356790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.keymgr_cfg_regwen.22196367005701343982458837045911479613211546445654517834418132013911689016665
Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 2150681 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 2150681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/cov_report/cov_report.log