KMAC/MASKED Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 0.840s 3.128us 0 50 0.00
V1 csr_hw_reset kmac_csr_hw_reset 0.730s 5.370us 0 5 0.00
V1 csr_rw kmac_csr_rw 0.790s 8.901us 0 20 0.00
V1 csr_bit_bash kmac_csr_bit_bash 0.740s 4.669us 0 5 0.00
V1 csr_aliasing kmac_csr_aliasing 0.760s 2.498us 0 5 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 0.860s 8.102us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 0.790s 8.901us 0 20 0.00
kmac_csr_aliasing 0.760s 2.498us 0 5 0.00
V1 mem_walk kmac_mem_walk 0.720s 30.186us 0 5 0.00
V1 mem_partial_access kmac_mem_partial_access 0.800s 1.089us 0 5 0.00
V1 TOTAL 0 115 0.00
V2 long_msg_and_output kmac_long_msg_and_output 0.800s 4.842us 0 50 0.00
V2 burst_write kmac_burst_write 0.830s 13.220us 0 50 0.00
V2 test_vectors kmac_test_vectors_sha3_224 0.770s 1.966us 0 5 0.00
kmac_test_vectors_sha3_256 0.780s 3.073us 0 5 0.00
kmac_test_vectors_sha3_384 0.780s 2.797us 0 5 0.00
kmac_test_vectors_sha3_512 0.780s 1.873us 0 5 0.00
kmac_test_vectors_shake_128 0.780s 3.628us 0 5 0.00
kmac_test_vectors_shake_256 0.780s 3.619us 0 5 0.00
kmac_test_vectors_kmac 0.780s 2.627us 0 5 0.00
kmac_test_vectors_kmac_xof 0.800s 8.164us 0 5 0.00
V2 sideload kmac_sideload 0.780s 5.235us 0 50 0.00
V2 app kmac_app 0.810s 3.694us 0 50 0.00
V2 app_with_partial_data kmac_app_with_partial_data 0.800s 2.583us 0 10 0.00
V2 entropy_refresh kmac_entropy_refresh 0.800s 4.650us 0 50 0.00
V2 error kmac_error 0.820s 823.219ns 0 50 0.00
V2 key_error kmac_key_error 0.790s 2.104us 0 50 0.00
V2 sideload_invalid kmac_sideload_invalid 0.820s 12.427us 0 50 0.00
V2 edn_timeout_error kmac_edn_timeout_error 0.810s 1.761us 0 20 0.00
V2 entropy_mode_error kmac_entropy_mode_error 0.810s 4.763us 0 20 0.00
V2 entropy_ready_error kmac_entropy_ready_error 0.800s 28.126us 0 10 0.00
V2 lc_escalation kmac_lc_escalation 0.840s 14.491us 0 50 0.00
V2 stress_all kmac_stress_all 0.810s 4.892us 0 50 0.00
V2 intr_test kmac_intr_test 0.850s 8.515us 0 50 0.00
V2 alert_test kmac_alert_test 0.830s 6.786us 0 50 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 0.790s 8.531us 0 20 0.00
V2 tl_d_illegal_access kmac_tl_errors 0.790s 8.531us 0 20 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0.730s 5.370us 0 5 0.00
kmac_csr_rw 0.790s 8.901us 0 20 0.00
kmac_csr_aliasing 0.760s 2.498us 0 5 0.00
kmac_same_csr_outstanding 0.810s 2.837us 0 20 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 0.730s 5.370us 0 5 0.00
kmac_csr_rw 0.790s 8.901us 0 20 0.00
kmac_csr_aliasing 0.760s 2.498us 0 5 0.00
kmac_same_csr_outstanding 0.810s 2.837us 0 20 0.00
V2 TOTAL 0 740 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 0.790s 1.663us 0 20 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 0.790s 1.663us 0 20 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 0.790s 1.663us 0 20 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 0.790s 1.663us 0 20 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 0.800s 1.756us 0 20 0.00
V2S tl_intg_err kmac_sec_cm 0.770s 3.701us 0 5 0.00
kmac_tl_intg_err 0.820s 1.768us 0 20 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 0.820s 1.768us 0 20 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 0.840s 14.491us 0 50 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 0.840s 3.128us 0 50 0.00
V2S sec_cm_key_sideload kmac_sideload 0.780s 5.235us 0 50 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 0.790s 1.663us 0 20 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 0.770s 3.701us 0 5 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 0.770s 3.701us 0 5 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 0.770s 3.701us 0 5 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 0.840s 3.128us 0 50 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 0.840s 14.491us 0 50 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 0.770s 3.701us 0 5 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 0.810s 1.292us 0 10 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 0.840s 3.128us 0 50 0.00
V2S TOTAL 0 75 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 0.800s 3.251us 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 0 940 0.00

Failure Buckets