KMAC/UNMASKED Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 0.900s 2.807us 0 50 0.00
V1 csr_hw_reset kmac_csr_hw_reset 0.640s 1.717us 0 5 0.00
V1 csr_rw kmac_csr_rw 0.910s 2.577us 0 20 0.00
V1 csr_bit_bash kmac_csr_bit_bash 0.660s 2.489us 0 5 0.00
V1 csr_aliasing kmac_csr_aliasing 0.630s 3.937us 0 5 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 0.940s 6.785us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 0.910s 2.577us 0 20 0.00
kmac_csr_aliasing 0.630s 3.937us 0 5 0.00
V1 mem_walk kmac_mem_walk 0.670s 27.729us 0 5 0.00
V1 mem_partial_access kmac_mem_partial_access 0.640s 4.631us 0 5 0.00
V1 TOTAL 0 115 0.00
V2 long_msg_and_output kmac_long_msg_and_output 0.890s 8.633us 0 50 0.00
V2 burst_write kmac_burst_write 0.920s 6.546us 0 50 0.00
V2 test_vectors kmac_test_vectors_sha3_224 0.910s 2.949us 0 5 0.00
kmac_test_vectors_sha3_256 0.920s 8.582us 0 5 0.00
kmac_test_vectors_sha3_384 0.840s 1.824us 0 5 0.00
kmac_test_vectors_sha3_512 0.920s 2.832us 0 5 0.00
kmac_test_vectors_shake_128 1.040s 9.018us 0 5 0.00
kmac_test_vectors_shake_256 1.010s 5.381us 0 5 0.00
kmac_test_vectors_kmac 0.830s 5.374us 0 5 0.00
kmac_test_vectors_kmac_xof 0.990s 1.021us 0 5 0.00
V2 sideload kmac_sideload 0.980s 960.938ns 0 50 0.00
V2 app kmac_app 0.880s 5.019us 0 50 0.00
V2 app_with_partial_data kmac_app_with_partial_data 0.820s 4.868us 0 10 0.00
V2 entropy_refresh kmac_entropy_refresh 0.760s 1.240us 0 50 0.00
V2 error kmac_error 0.760s 2.715us 0 50 0.00
V2 key_error kmac_key_error 0.730s 4.519us 0 50 0.00
V2 sideload_invalid kmac_sideload_invalid 0.980s 4.894us 0 50 0.00
V2 edn_timeout_error kmac_edn_timeout_error 0.690s 1.205us 0 20 0.00
V2 entropy_mode_error kmac_entropy_mode_error 0.720s 1.198us 0 20 0.00
V2 entropy_ready_error kmac_entropy_ready_error 0.810s 6.268us 0 10 0.00
V2 lc_escalation kmac_lc_escalation 0.710s 3.852us 0 50 0.00
V2 stress_all kmac_stress_all 0.680s 4.755us 0 50 0.00
V2 intr_test kmac_intr_test 0.930s 3.866us 0 50 0.00
V2 alert_test kmac_alert_test 0.710s 14.789us 0 50 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 0.810s 7.956us 0 20 0.00
V2 tl_d_illegal_access kmac_tl_errors 0.810s 7.956us 0 20 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0.640s 1.717us 0 5 0.00
kmac_csr_rw 0.910s 2.577us 0 20 0.00
kmac_csr_aliasing 0.630s 3.937us 0 5 0.00
kmac_same_csr_outstanding 0.830s 27.854us 0 20 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 0.640s 1.717us 0 5 0.00
kmac_csr_rw 0.910s 2.577us 0 20 0.00
kmac_csr_aliasing 0.630s 3.937us 0 5 0.00
kmac_same_csr_outstanding 0.830s 27.854us 0 20 0.00
V2 TOTAL 0 740 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 0.820s 4.777us 0 20 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 0.820s 4.777us 0 20 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 0.820s 4.777us 0 20 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 0.820s 4.777us 0 20 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 0.860s 6.553us 0 20 0.00
V2S tl_intg_err kmac_sec_cm 0.800s 1.660us 0 5 0.00
kmac_tl_intg_err 0.890s 4.328us 0 20 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 0.890s 4.328us 0 20 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 0.710s 3.852us 0 50 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 0.900s 2.807us 0 50 0.00
V2S sec_cm_key_sideload kmac_sideload 0.980s 960.938ns 0 50 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 0.820s 4.777us 0 20 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 0.800s 1.660us 0 5 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 0.800s 1.660us 0 5 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 0.800s 1.660us 0 5 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 0.900s 2.807us 0 50 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 0.710s 3.852us 0 50 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 0.800s 1.660us 0 5 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 0.780s 21.467us 0 10 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 0.900s 2.807us 0 50 0.00
V2S TOTAL 0 75 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 0.810s 2.507us 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 0 940 0.00

Failure Buckets