751b8fb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 22.317m | 200.000ms | 0 | 2 | 0.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 50.650m | 200.000ms | 0 | 5 | 0.00 |
| V1 | csr_rw | mbx_csr_rw | 49.867m | 200.000ms | 0 | 20 | 0.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 55.983m | 200.000ms | 0 | 5 | 0.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 50.833m | 200.000ms | 0 | 5 | 0.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 49.867m | 200.000ms | 0 | 20 | 0.00 |
| mbx_csr_aliasing | 50.833m | 200.000ms | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 57 | 0.00 | |||
| V2 | mbx_stress | mbx_stress | 59.383m | 200.000ms | 0 | 2 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 42.767m | 200.000ms | 0 | 2 | 0.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 41.183m | 200.000ms | 0 | 2 | 0.00 |
| V2 | alert_test | mbx_alert_test | 58.433m | 200.000ms | 0 | 50 | 0.00 |
| V2 | intr_test | mbx_intr_test | 55.583m | 200.000ms | 0 | 50 | 0.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 49.300m | 200.000ms | 0 | 20 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 49.300m | 200.000ms | 0 | 20 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 50.650m | 200.000ms | 0 | 5 | 0.00 |
| mbx_csr_rw | 49.867m | 200.000ms | 0 | 20 | 0.00 | ||
| mbx_csr_aliasing | 50.833m | 200.000ms | 0 | 5 | 0.00 | ||
| mbx_same_csr_outstanding | 57.083m | 200.000ms | 0 | 20 | 0.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 50.650m | 200.000ms | 0 | 5 | 0.00 |
| mbx_csr_rw | 49.867m | 200.000ms | 0 | 20 | 0.00 | ||
| mbx_csr_aliasing | 50.833m | 200.000ms | 0 | 5 | 0.00 | ||
| mbx_same_csr_outstanding | 57.083m | 200.000ms | 0 | 20 | 0.00 | ||
| V2 | TOTAL | 0 | 146 | 0.00 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 59.050m | 200.000ms | 0 | 20 | 0.00 |
| mbx_sec_cm | 32.783m | 200.000ms | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| TOTAL | 0 | 228 | 0.00 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 168 failures:
Test mbx_smoke has 1 failures.
0.mbx_smoke.51242628229844108693693606907990484030878123665541917459915265802113818511632
Line 922, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_smoke/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_stress has 2 failures.
0.mbx_stress.100265125950681208889552688079966598987060847211849390952567704011481848974708
Line 3090, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.mbx_stress.34807490347867280228624735413499443499667665954364593907507475072775140313605
Line 1160, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_stress_zero_delays has 2 failures.
0.mbx_stress_zero_delays.18978289258882648355913749877972801001067957554782045680466347265639124435912
Line 1256, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.mbx_stress_zero_delays.36283760258617259124278721816120785965729326609178083713898270694763909819290
Line 2366, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_imbx_oob has 2 failures.
0.mbx_imbx_oob.9497365404374915180184276116939625076987593244923589293986000092982056904471
Line 1648, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.mbx_imbx_oob.61070778273737470164323659825754971581403358963615559372532501389191365309377
Line 2368, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_imbx_oob/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_tl_errors has 15 failures.
0.mbx_tl_errors.113524457604909897684999824672408538832129323454375858764796024586431578221891
Line 490, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.mbx_tl_errors.16450187221420225679339600065207261459853696846620284615001671263952112478323
Line 2558, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_tl_errors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
... and 9 more tests.
Job timed out after * minutes has 59 failures:
Test mbx_sec_cm has 3 failures.
0.mbx_sec_cm.82101382542252134163575986793207685873617702142619434543462558648790478306744
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_sec_cm/latest/run.log
Job timed out after 60 minutes
2.mbx_sec_cm.76320543140835298891703442842679370813653912120392971405089142826153149236090
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_sec_cm/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test mbx_csr_rw has 6 failures.
0.mbx_csr_rw.22293336418668938466262762574872100183201704573105518972769445934967308047085
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_rw/latest/run.log
Job timed out after 60 minutes
4.mbx_csr_rw.57391138933545354401429484935950449925451961768323948469567134960714887263432
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_csr_rw/latest/run.log
Job timed out after 60 minutes
... and 4 more failures.
Test mbx_csr_mem_rw_with_rand_reset has 20 failures.
0.mbx_csr_mem_rw_with_rand_reset.47306335206577141337871573324209414263818613731438933662033688375126984964694
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
Job timed out after 60 minutes
1.mbx_csr_mem_rw_with_rand_reset.13257001738335675187662344346506352863537679305014719940566255887287973642302
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_csr_mem_rw_with_rand_reset/latest/run.log
Job timed out after 60 minutes
... and 18 more failures.
Test mbx_smoke has 1 failures.
1.mbx_smoke.83008154444589872883650350362428084424433783120788148556393943117596907305224
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_smoke/latest/run.log
Job timed out after 60 minutes
Test mbx_csr_hw_reset has 2 failures.
1.mbx_csr_hw_reset.112325916319476768611366219704788640555320085078187918865353608680322320372537
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_csr_hw_reset/latest/run.log
Job timed out after 60 minutes
4.mbx_csr_hw_reset.33334540224759728007124521608857530925130620825756079817172816009874807139928
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_csr_hw_reset/latest/run.log
Job timed out after 60 minutes
... and 6 more tests.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/cov_merge/merged/cov_merge.log
cov_report
Log /nightly/current_run/scratch/master/mbx-sim-xcelium/cov_report/cov_report.log
UVM_ERROR (mbx_base_vseq.sv:602) virtual_sequencer [_item] Response DWORD mismatches q[*](*) != rsp[*](*) has 1 failures:
5.mbx_tl_intg_err.97832115487204487736214654085727331939346508652095158233535408437817872614883
Line 84, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 408833688 ps: (mbx_base_vseq.sv:602) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer._item] Response DWORD mismatches q[405]('he57514d2) != rsp[405]('h2549064b)
UVM_INFO @ 408833688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---