751b8fb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.680s | 978.798ns | 0 | 2 | 0.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 2.130s | 16.614us | 0 | 5 | 0.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 2.080s | 2.572us | 0 | 20 | 0.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 1.900s | 18.973us | 0 | 5 | 0.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 2.140s | 2.386us | 0 | 5 | 0.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 2.340s | 5.134us | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 2.080s | 2.572us | 0 | 20 | 0.00 |
| rom_ctrl_csr_aliasing | 2.140s | 2.386us | 0 | 5 | 0.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 2.210s | 10.945us | 0 | 5 | 0.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 2.070s | 2.129us | 0 | 5 | 0.00 |
| V1 | TOTAL | 0 | 67 | 0.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 1.560s | 6.176us | 0 | 2 | 0.00 |
| V2 | stress_all | rom_ctrl_stress_all | 1.770s | 19.502us | 0 | 20 | 0.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.510s | 2.512us | 0 | 2 | 0.00 |
| V2 | alert_test | rom_ctrl_alert_test | 1.930s | 3.411us | 0 | 50 | 0.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 2.100s | 883.032ns | 0 | 20 | 0.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 2.100s | 883.032ns | 0 | 20 | 0.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 2.130s | 16.614us | 0 | 5 | 0.00 |
| rom_ctrl_csr_rw | 2.080s | 2.572us | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 2.140s | 2.386us | 0 | 5 | 0.00 | ||
| rom_ctrl_same_csr_outstanding | 2.200s | 3.290us | 0 | 20 | 0.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 2.130s | 16.614us | 0 | 5 | 0.00 |
| rom_ctrl_csr_rw | 2.080s | 2.572us | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 2.140s | 2.386us | 0 | 5 | 0.00 | ||
| rom_ctrl_same_csr_outstanding | 2.200s | 3.290us | 0 | 20 | 0.00 | ||
| V2 | TOTAL | 0 | 114 | 0.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 2.280s | 3.648us | 0 | 20 | 0.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.830s | 2.962us | 0 | 5 | 0.00 |
| rom_ctrl_tl_intg_err | 2.030s | 2.203us | 0 | 20 | 0.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.830s | 2.962us | 0 | 5 | 0.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 1.830s | 2.962us | 0 | 5 | 0.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.830s | 2.962us | 0 | 5 | 0.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.830s | 2.962us | 0 | 5 | 0.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.680s | 978.798ns | 0 | 2 | 0.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.680s | 978.798ns | 0 | 2 | 0.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.680s | 978.798ns | 0 | 2 | 0.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.030s | 2.203us | 0 | 20 | 0.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| rom_ctrl_kmac_err_chk | 1.510s | 2.512us | 0 | 2 | 0.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 1.780s | 2.789us | 0 | 20 | 0.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 2.280s | 3.648us | 0 | 20 | 0.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.830s | 2.962us | 0 | 5 | 0.00 |
| V2S | TOTAL | 0 | 65 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 1.800s | 12.081us | 0 | 20 | 0.00 |
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| TOTAL | 0 | 266 | 0.00 |
UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class! has 266 failures:
Test rom_ctrl_smoke has 2 failures.
0.rom_ctrl_smoke.4053047221696692566193820171509093625500109097970617085986415328423765751265
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 5016348 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 5016348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_smoke.102019135433411246184164285459506233688019755872521387376547071075464085918476
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 978798 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 978798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all has 20 failures.
0.rom_ctrl_stress_all.58007654228077561380083404916844579353238962168475923029658843578639829464498
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 1102565 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 1102565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all.71822270533252649718151890587668206117068106851941724802518380815240158280029
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 13313237 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 13313237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rom_ctrl_max_throughput_chk has 2 failures.
0.rom_ctrl_max_throughput_chk.61936193866629243917647660534274281508496200631838045696557356598125571430523
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log
UVM_FATAL @ 6176195 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 6176195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_max_throughput_chk.7927036380993810583235708824749962410433821401124216084006846153165986347438
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
UVM_FATAL @ 8243939 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 8243939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_corrupt_sig_fatal_chk has 20 failures.
0.rom_ctrl_corrupt_sig_fatal_chk.15019984283713746738699856988255330991785471661425338223619808573889894531419
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 3491640 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 3491640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_corrupt_sig_fatal_chk.109677365800371836924241138466732006793950156713219861474336822585483886694242
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 6738774 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 6738774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rom_ctrl_kmac_err_chk has 2 failures.
0.rom_ctrl_kmac_err_chk.15228439799619064206056064215870015274084709079546818930517435486827948780252
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log
UVM_FATAL @ 2643870 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 2643870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_kmac_err_chk.78537302649570371470546789885839707591394718011433735391025217301888805106704
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
UVM_FATAL @ 2511955 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 2511955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more tests.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/cov_report/cov_report.log