751b8fb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 3.770s | 2.955us | 0 | 2 | 0.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 2.510s | 2.286us | 0 | 5 | 0.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 2.500s | 2.118us | 0 | 20 | 0.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 2.380s | 902.408ns | 0 | 5 | 0.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 2.270s | 3.996us | 0 | 5 | 0.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 2.240s | 5.654us | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 2.500s | 2.118us | 0 | 20 | 0.00 |
| rom_ctrl_csr_aliasing | 2.270s | 3.996us | 0 | 5 | 0.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 2.660s | 15.956us | 0 | 5 | 0.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 2.640s | 14.977us | 0 | 5 | 0.00 |
| V1 | TOTAL | 0 | 67 | 0.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 3.800s | 2.999us | 0 | 2 | 0.00 |
| V2 | stress_all | rom_ctrl_stress_all | 2.950s | 19.798us | 0 | 20 | 0.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 3.790s | 9.169us | 0 | 2 | 0.00 |
| V2 | alert_test | rom_ctrl_alert_test | 3.150s | 1.530us | 0 | 50 | 0.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 2.530s | 22.179us | 0 | 20 | 0.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 2.530s | 22.179us | 0 | 20 | 0.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 2.510s | 2.286us | 0 | 5 | 0.00 |
| rom_ctrl_csr_rw | 2.500s | 2.118us | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 2.270s | 3.996us | 0 | 5 | 0.00 | ||
| rom_ctrl_same_csr_outstanding | 2.460s | 4.092us | 0 | 20 | 0.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 2.510s | 2.286us | 0 | 5 | 0.00 |
| rom_ctrl_csr_rw | 2.500s | 2.118us | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 2.270s | 3.996us | 0 | 5 | 0.00 | ||
| rom_ctrl_same_csr_outstanding | 2.460s | 4.092us | 0 | 20 | 0.00 | ||
| V2 | TOTAL | 0 | 114 | 0.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 2.600s | 3.614us | 0 | 20 | 0.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.440s | 2.398us | 0 | 5 | 0.00 |
| rom_ctrl_tl_intg_err | 2.460s | 5.932us | 0 | 20 | 0.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.440s | 2.398us | 0 | 5 | 0.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 3.440s | 2.398us | 0 | 5 | 0.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.440s | 2.398us | 0 | 5 | 0.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.440s | 2.398us | 0 | 5 | 0.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 3.770s | 2.955us | 0 | 2 | 0.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 3.770s | 2.955us | 0 | 2 | 0.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 3.770s | 2.955us | 0 | 2 | 0.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.460s | 5.932us | 0 | 20 | 0.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| rom_ctrl_kmac_err_chk | 3.790s | 9.169us | 0 | 2 | 0.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 2.810s | 960.618ns | 0 | 20 | 0.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 2.600s | 3.614us | 0 | 20 | 0.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.440s | 2.398us | 0 | 5 | 0.00 |
| V2S | TOTAL | 0 | 65 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 3.050s | 1.966us | 0 | 20 | 0.00 |
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| TOTAL | 0 | 266 | 0.00 |
UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class! has 266 failures:
Test rom_ctrl_smoke has 2 failures.
0.rom_ctrl_smoke.114745316372197832762827251025421298872436897439879440279822664450967375720390
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 2954795 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 2954795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_smoke.9301793180443526625860769014720727227213289945399777997428276886010456413950
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest/run.log
UVM_FATAL @ 1044647 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 1044647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all has 20 failures.
0.rom_ctrl_stress_all.90421103278639449710986234190861995141891852941454486773392377661096434604603
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 1705552 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 1705552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all.9258568870787631977513496035604072232457471468707028487158761575413791523840
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
UVM_FATAL @ 12275129 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 12275129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rom_ctrl_max_throughput_chk has 2 failures.
0.rom_ctrl_max_throughput_chk.62040746570364857674826243876595743578660706888501088899224749376973883064237
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log
UVM_FATAL @ 3772174 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 3772174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_max_throughput_chk.92377693086003864393411265231652593983389750799809433117106795495604759752674
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
UVM_FATAL @ 2999017 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 2999017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_corrupt_sig_fatal_chk has 20 failures.
0.rom_ctrl_corrupt_sig_fatal_chk.77112736357546431516329437937245820883890907914533039799464224955646027033544
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 4860527 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 4860527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_corrupt_sig_fatal_chk.75840276132507456328422817589001799438367825755504186831080389770240959948114
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_FATAL @ 6240935 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 6240935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rom_ctrl_kmac_err_chk has 2 failures.
0.rom_ctrl_kmac_err_chk.19540213344093202823016880766803639755091993662781410284359383639206053177199
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log
UVM_FATAL @ 3049163 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 3049163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_kmac_err_chk.111565334979541939727747388107623354968352188721957628594787480715343290998976
Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
UVM_FATAL @ 9169491 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 9169491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more tests.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/cov_report/cov_report.log