RV_DM/USE_DMI_INTERFACE Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	0.800s	72.679us	0	2	0.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	0.840s	132.225us	0	5	0.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	0.850s	29.849us	0	20	0.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	0.750s	69.790us	0	5	0.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	0.730s	121.261us	0	5	0.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	0.920s	63.864us	0	5	0.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	0.820s	130.711us	0	20	0.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.020s	129.031us	0	20	0.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	0.850s	62.753us	0	5	0.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	0.740s	17.657us	0	2	0.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.880s	108.585us	0	2	0.00
V1	cmderr_exception	rv_dm_cmderr_exception	0.770s	106.466us	0	2	0.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	0.780s	94.979us	0	2	0.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.800s	53.060us	0	2	0.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	0.730s	38.412us	0	2	0.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.780s	18.940us	0	2	0.00
V1	halt_resume	rv_dm_halt_resume_whereto	0.830s	76.659us	0	8	0.00
V1	progbuf_busy	rv_dm_cmderr_busy	0.740s	17.657us	0	2	0.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.800s	74.055us	0	2	0.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	0.720s	58.689us	0	2	0.00
V1	progbuf_exception	rv_dm_cmderr_exception	0.770s	106.466us	0	2	0.00
V1	rom_read_access	rv_dm_rom_read_access	0.730s	188.734us	0	2	0.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.000s	125.406us	0	5	0.00
V1	csr_rw	rv_dm_csr_rw	0.930s	124.722us	0	20	0.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.090s	133.578us	0	5	0.00
V1	csr_aliasing	rv_dm_csr_aliasing	0.760s	141.469us	0	5	0.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	0.780s	172.384us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	0.760s	141.469us	0	5	0.00
		rv_dm_csr_rw	0.930s	124.722us	0	20	0.00
V1	mem_walk	rv_dm_mem_walk	0.770s	62.278us	0	5	0.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.750s	37.804us	0	5	0.00
V1		TOTAL			0	180	0.00
V2	idcode	rv_dm_smoke	0.800s	72.679us	0	2	0.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.720s	117.331us	0	2	0.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.710s	95.681us	0	2	0.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.720s	126.924us	0	2	0.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	0.700s	110.145us	0	2	0.00
V2	sba	rv_dm_sba_tl_access	0.980s	152.558us	0	20	0.00
		rv_dm_delayed_resp_sba_tl_access	0.970s	65.497us	0	20	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	0.840s	90.801us	0	20	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	0.850s	124.109us	0	20	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.760s	53.348us	0	2	0.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	0.680s	84.634us	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.660s	43.711us	0	2	0.00
V2	hart_unavail	rv_dm_hart_unavail	0.950s	94.054us	0	5	0.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	0.670s	42.992us	0	1	0.00
		rv_dm_tap_fsm_rand_reset	0.780s	69.773us	0	10	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.650s	38.795us	0	1	0.00
V2	stress_all	rv_dm_stress_all	0.970s	141.364us	0	50	0.00
V2	alert_test	rv_dm_alert_test	1.090s	135.201us	0	50	0.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	0.880s	92.942us	0	20	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	0.880s	92.942us	0	20	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	0.760s	141.469us	0	5	0.00
		rv_dm_csr_hw_reset	1.000s	125.406us	0	5	0.00
		rv_dm_csr_rw	0.930s	124.722us	0	20	0.00
		rv_dm_same_csr_outstanding	0.840s	92.848us	0	20	0.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	0.760s	141.469us	0	5	0.00
		rv_dm_csr_hw_reset	1.000s	125.406us	0	5	0.00
		rv_dm_csr_rw	0.930s	124.722us	0	20	0.00
		rv_dm_same_csr_outstanding	0.840s	92.848us	0	20	0.00
V2		TOTAL			0	251	0.00
V2S	tl_intg_err	rv_dm_sec_cm	0.660s	28.929us	0	5	0.00
		rv_dm_tl_intg_err	1.040s	136.875us	0	20	0.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	1.040s	136.875us	0	20	0.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	0.680s	84.634us	0	2	0.00
		rv_dm_debug_disabled	0.650s	52.086us	0	2	0.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	0.680s	84.634us	0	2	0.00
		rv_dm_debug_disabled	0.650s	52.086us	0	2	0.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	0.800s	72.679us	0	2	0.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	0.920s	135.829us	0	10	0.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.790s	87.396us	0	4	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.790s	87.396us	0	4	0.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	0.920s	135.829us	0	10	0.00
V2S		TOTAL			0	41	0.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	0.950s	113.812us	0	10	0.00
V3		TOTAL			0	10	0.00
	Unmapped tests	rv_dm_scanmode	0.640s	23.736us	0	1	0.00
		TOTAL			0	483	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class! has 483 failures:

  • Test rv_dm_csr_aliasing has 5 failures.

    • 0.rv_dm_csr_aliasing.76290440960106322370404459041747703937692654985245859664158927125190656527661
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log

        UVM_FATAL @ 141468913 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @ 141468913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_csr_aliasing.19079499076590538970604228294698964739108142418920140299471553903274365577274
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest/run.log

        UVM_FATAL @ 115967591 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @ 115967591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test rv_dm_smoke has 2 failures.

    • 0.rv_dm_smoke.84658180782112860237898447555966305286061722252574679476262243831298994968811
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log

        UVM_FATAL @  72678709 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  72678709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_smoke.34565063275507948100618906868296196277963222235378241445001798969256567860388
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_smoke/latest/run.log

        UVM_FATAL @  81750889 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  81750889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_tap_fsm has 1 failures.

    • 0.rv_dm_tap_fsm.107416129094796311558577229381291383883610548841516677158210112654196950150509
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

        UVM_FATAL @  42991972 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  42991972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.

    • 0.rv_dm_jtag_dtm_csr_hw_reset.33135240307127732080595515837205983077569464550706938531722550736600053242319
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

        UVM_FATAL @  24962553 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  24962553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_jtag_dtm_csr_hw_reset.157786318475234626440579245551795714114335083832370387855777539721157143940
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

        UVM_FATAL @ 132224936 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @ 132224936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test rv_dm_jtag_dtm_csr_rw has 20 failures.

    • 0.rv_dm_jtag_dtm_csr_rw.99827438560558290687962241719644944674311313274521575405558049903543947632583
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log

        UVM_FATAL @  22295689 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  22295689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_jtag_dtm_csr_rw.69355392625962831616933226997291071714595225642538975959488151497857072254029
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest/run.log

        UVM_FATAL @  33637837 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  33637837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 18 more failures.

  • ... and 48 more tests.

• Job killed most likely because its dependent job failed. has 2 failures:
  • Test rv_dm has 2 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/cov_merge/merged.vdb/cov_merge.log

    • cov_report
      Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/cov_report/cov_report.log