SPI_DEVICE/1R1W Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 0.810s 3.632us 0 50 0.00
V1 csr_hw_reset spi_device_csr_hw_reset 0.620s 2.120us 0 5 0.00
V1 csr_rw spi_device_csr_rw 0.810s 1.694us 0 20 0.00
V1 csr_bit_bash spi_device_csr_bit_bash 0.640s 2.077us 0 5 0.00
V1 csr_aliasing spi_device_csr_aliasing 0.640s 5.643us 0 5 0.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 0.760s 782.218ns 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 0.810s 1.694us 0 20 0.00
spi_device_csr_aliasing 0.640s 5.643us 0 5 0.00
V1 mem_walk spi_device_mem_walk 0.620s 4.059us 0 5 0.00
V1 mem_partial_access spi_device_mem_partial_access 0.650s 752.540ns 0 5 0.00
V1 TOTAL 0 115 0.00
V2 csb_read spi_device_csb_read 0.810s 7.130us 0 50 0.00
V2 mem_parity spi_device_mem_parity 0.810s 914.922ns 0 20 0.00
V2 mem_cfg spi_device_ram_cfg 0.660s 6.086us 0 1 0.00
V2 tpm_read spi_device_tpm_rw 0.850s 1.665us 0 50 0.00
V2 tpm_write spi_device_tpm_rw 0.850s 1.665us 0 50 0.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 0.820s 1.238us 0 50 0.00
spi_device_tpm_sts_read 0.850s 927.596ns 0 50 0.00
V2 tpm_fully_random_case spi_device_tpm_all 0.830s 923.855ns 0 50 0.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 0.840s 1.618us 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 0.780s 2.163us 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 0.780s 2.163us 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 cmd_info_slots spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 cmd_read_status spi_device_intercept 0.840s 915.799ns 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 cmd_read_jedec spi_device_intercept 0.840s 915.799ns 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 cmd_read_sfdp spi_device_intercept 0.840s 915.799ns 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 cmd_fast_read spi_device_intercept 0.840s 915.799ns 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 cmd_read_pipeline spi_device_intercept 0.840s 915.799ns 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 flash_cmd_upload spi_device_upload 0.820s 852.120ns 0 50 0.00
V2 mailbox_command spi_device_mailbox 0.760s 2.178us 0 50 0.00
V2 mailbox_cross_outside_command spi_device_mailbox 0.760s 2.178us 0 50 0.00
V2 mailbox_cross_inside_command spi_device_mailbox 0.760s 2.178us 0 50 0.00
V2 cmd_read_buffer spi_device_flash_mode 0.850s 1.605us 0 50 0.00
spi_device_read_buffer_direct 0.830s 912.790ns 0 50 0.00
V2 cmd_dummy_cycle spi_device_mailbox 0.760s 2.178us 0 50 0.00
spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 quad_spi spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 dual_spi spi_device_flash_all 0.820s 1.131us 0 50 0.00
V2 4b_3b_feature spi_device_cfg_cmd 0.790s 2.126us 0 50 0.00
V2 write_enable_disable spi_device_cfg_cmd 0.790s 2.126us 0 50 0.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 0.810s 3.632us 0 50 0.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 0.770s 4.324us 0 50 0.00
V2 stress_all spi_device_stress_all 0.820s 1.092us 0 50 0.00
V2 alert_test spi_device_alert_test 0.820s 4.226us 0 50 0.00
V2 intr_test spi_device_intr_test 0.930s 5.739us 0 50 0.00
V2 tl_d_oob_addr_access spi_device_tl_errors 0.810s 963.196ns 0 20 0.00
V2 tl_d_illegal_access spi_device_tl_errors 0.810s 963.196ns 0 20 0.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 0.620s 2.120us 0 5 0.00
spi_device_csr_rw 0.810s 1.694us 0 20 0.00
spi_device_csr_aliasing 0.640s 5.643us 0 5 0.00
spi_device_same_csr_outstanding 0.810s 1.680us 0 20 0.00
V2 tl_d_partial_access spi_device_csr_hw_reset 0.620s 2.120us 0 5 0.00
spi_device_csr_rw 0.810s 1.694us 0 20 0.00
spi_device_csr_aliasing 0.640s 5.643us 0 5 0.00
spi_device_same_csr_outstanding 0.810s 1.680us 0 20 0.00
V2 TOTAL 0 961 0.00
V2S tl_intg_err spi_device_sec_cm 0.770s 2.756us 0 5 0.00
spi_device_tl_intg_err 0.810s 3.113us 0 20 0.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 0.810s 3.113us 0 20 0.00
V2S TOTAL 0 25 0.00
Unmapped tests spi_device_flash_mode_ignore_cmds 0.810s 9.638us 0 50 0.00
TOTAL 0 1151 0.00

Failure Buckets