SRAM_CTRL/RET Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 1.060s 0 50 0.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.850s 0 5 0.00
V1 csr_rw sram_ctrl_csr_rw 0.870s 0 20 0.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 0.780s 0 5 0.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.710s 0 5 0.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 0.760s 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.870s 0 20 0.00
sram_ctrl_csr_aliasing 0.710s 0 5 0.00
V1 mem_walk sram_ctrl_mem_walk 1.050s 0 50 0.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.040s 0 50 0.00
V1 TOTAL 0 205 0.00
V2 multiple_keys sram_ctrl_multiple_keys 1.030s 0 50 0.00
V2 stress_pipeline sram_ctrl_stress_pipeline 1.110s 0 50 0.00
V2 bijection sram_ctrl_bijection 1.040s 0 50 0.00
V2 access_during_key_req sram_ctrl_access_during_key_req 1.040s 0 50 0.00
V2 lc_escalation sram_ctrl_lc_escalation 1.110s 0 50 0.00
V2 executable sram_ctrl_executable 1.040s 0 50 0.00
V2 partial_access sram_ctrl_partial_access 1.110s 0 50 0.00
sram_ctrl_partial_access_b2b 1.060s 0 50 0.00
V2 max_throughput sram_ctrl_max_throughput 1.070s 0 50 0.00
sram_ctrl_throughput_w_partial_write 1.040s 0 50 0.00
sram_ctrl_throughput_w_readback 1.060s 0 50 0.00
V2 regwen sram_ctrl_regwen 1.090s 0 50 0.00
V2 ram_cfg sram_ctrl_ram_cfg 0.990s 0 50 0.00
V2 stress_all sram_ctrl_stress_all 1.090s 0 50 0.00
V2 alert_test sram_ctrl_alert_test 1.030s 0 50 0.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 0.900s 0 20 0.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 0.900s 0 20 0.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.850s 0 5 0.00
sram_ctrl_csr_rw 0.870s 0 20 0.00
sram_ctrl_csr_aliasing 0.710s 0 5 0.00
sram_ctrl_same_csr_outstanding 0.810s 0 20 0.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.850s 0 5 0.00
sram_ctrl_csr_rw 0.870s 0 20 0.00
sram_ctrl_csr_aliasing 0.710s 0 5 0.00
sram_ctrl_same_csr_outstanding 0.810s 0 20 0.00
V2 TOTAL 0 790 0.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 0.900s 0 20 0.00
V2S tl_intg_err sram_ctrl_sec_cm 0.590s 0 5 0.00
sram_ctrl_tl_intg_err 0.880s 0 20 0.00
V2S prim_count_check sram_ctrl_sec_cm 0.590s 0 5 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 0.880s 0 20 0.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 1.090s 0 50 0.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 1.090s 0 50 0.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.870s 0 20 0.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 1.040s 0 50 0.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 1.040s 0 50 0.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 1.040s 0 50 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.110s 0 50 0.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 1.020s 0 50 0.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 0.900s 0 20 0.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 1.040s 0 50 0.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 1.060s 0 50 0.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 1.060s 0 50 0.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 1.040s 0 50 0.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0.590s 0 5 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.110s 0 50 0.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0.590s 0 5 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0.590s 0 5 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 1.060s 0 50 0.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0.590s 0 5 0.00
V2S TOTAL 0 145 0.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.070s 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 0 1190 0.00

Failure Buckets