UART Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: 751b8fb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	0.630s	982.774ns	0	50	0.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	672.413ns	0	5	0.00
V1	csr_rw	uart_csr_rw	0.580s	2.552us	0	20	0.00
V1	csr_bit_bash	uart_csr_bit_bash	0.580s	846.863ns	0	5	0.00
V1	csr_aliasing	uart_csr_aliasing	0.620s	1.488us	0	5	0.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.600s	890.474ns	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.580s	2.552us	0	20	0.00
		uart_csr_aliasing	0.620s	1.488us	0	5	0.00
V1		TOTAL			0	105	0.00
V2	base_random_seq	uart_tx_rx	0.620s	2.698us	0	50	0.00
V2	parity	uart_smoke	0.630s	982.774ns	0	50	0.00
		uart_tx_rx	0.620s	2.698us	0	50	0.00
V2	parity_error	uart_intr	0.630s	1.142us	0	50	0.00
		uart_rx_parity_err	0.660s	1.087us	0	50	0.00
V2	watermark	uart_tx_rx	0.620s	2.698us	0	50	0.00
		uart_intr	0.630s	1.142us	0	50	0.00
V2	fifo_full	uart_fifo_full	0.630s	817.381ns	0	50	0.00
V2	fifo_overflow	uart_fifo_overflow	0.630s	1.194us	0	50	0.00
V2	fifo_reset	uart_fifo_reset	0.630s	2.599us	0	300	0.00
V2	rx_frame_err	uart_intr	0.630s	1.142us	0	50	0.00
V2	rx_break_err	uart_intr	0.630s	1.142us	0	50	0.00
V2	rx_timeout	uart_intr	0.630s	1.142us	0	50	0.00
V2	perf	uart_perf	0.640s	736.724ns	0	50	0.00
V2	sys_loopback	uart_loopback	0.650s	4.177us	0	50	0.00
V2	line_loopback	uart_loopback	0.650s	4.177us	0	50	0.00
V2	rx_noise_filter	uart_noise_filter	0.630s	898.598ns	0	50	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	0.630s	847.710ns	0	50	0.00
V2	tx_overide	uart_tx_ovrd	0.620s	3.500us	0	50	0.00
V2	rx_oversample	uart_rx_oversample	0.650s	15.165us	0	50	0.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	0.600s	1.656us	0	50	0.00
V2	stress_all	uart_stress_all	0.610s	14.467us	0	50	0.00
V2	alert_test	uart_alert_test	0.630s	3.653us	0	50	0.00
V2	intr_test	uart_intr_test	0.810s	1.669us	0	50	0.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.580s	698.573ns	0	20	0.00
V2	tl_d_illegal_access	uart_tl_errors	0.580s	698.573ns	0	20	0.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	672.413ns	0	5	0.00
		uart_csr_rw	0.580s	2.552us	0	20	0.00
		uart_csr_aliasing	0.620s	1.488us	0	5	0.00
		uart_same_csr_outstanding	0.600s	1.328us	0	20	0.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	672.413ns	0	5	0.00
		uart_csr_rw	0.580s	2.552us	0	20	0.00
		uart_csr_aliasing	0.620s	1.488us	0	5	0.00
		uart_same_csr_outstanding	0.600s	1.328us	0	20	0.00
V2		TOTAL			0	1090	0.00
V2S	tl_intg_err	uart_sec_cm	0.630s	955.338ns	0	5	0.00
		uart_tl_intg_err	0.580s	1.023us	0	20	0.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.580s	1.023us	0	20	0.00
V2S		TOTAL			0	25	0.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	0.620s	870.144ns	0	100	0.00
V3		TOTAL			0	100	0.00
		TOTAL			0	1320	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class! has 1320 failures:
  • Test uart_smoke has 50 failures.

    • 0.uart_smoke.48199407730452852125708730876668570648880380249497880782267257741389487037114
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_smoke/latest/run.log

        UVM_FATAL @   2044848 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2044848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.uart_smoke.58728536086310079766308966603646861224019117060985038423377732721022010740481
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_smoke/latest/run.log

        UVM_FATAL @    947950 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    947950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 48 more failures.

  • Test uart_tx_rx has 50 failures.

    • 0.uart_tx_rx.20306570851159033058875667924836236503393487039843919902900931747571401492522
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_tx_rx/latest/run.log

        UVM_FATAL @   2698221 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2698221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.uart_tx_rx.48463952404232047490911383639618437583270357263664826755121732935354179920665
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_tx_rx/latest/run.log

        UVM_FATAL @   3227430 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3227430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 48 more failures.

  • Test uart_fifo_full has 50 failures.

    • 0.uart_fifo_full.68984343220306147423944593259808230881175325010705668257593524812515500272364
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_full/latest/run.log

        UVM_FATAL @   1042743 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1042743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.uart_fifo_full.20690272402131849598611132440995409781863276178057111506179077060243928922458
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_fifo_full/latest/run.log

        UVM_FATAL @   6936711 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   6936711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 48 more failures.

  • Test uart_fifo_overflow has 50 failures.

    • 0.uart_fifo_overflow.2239241049451676847076174390918603964554949461743957506423960122569053552039
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_overflow/latest/run.log

        UVM_FATAL @   4218743 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   4218743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.uart_fifo_overflow.50872639912018528322801193738606296155489576518144883313561626261063454677643
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_fifo_overflow/latest/run.log

        UVM_FATAL @   1540702 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1540702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 48 more failures.

  • Test uart_fifo_reset has 300 failures.

    • 0.uart_fifo_reset.55837108514819187706183366174484150973437671550261446059484237692714332049190
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_reset/latest/run.log

        UVM_FATAL @   1005814 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1005814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.uart_fifo_reset.83111190941972325473318759192371398706708223573895988721206925640798865915338
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_fifo_reset/latest/run.log

        UVM_FATAL @   1749133 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1749133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 298 more failures.

  • ... and 22 more tests.
• Job killed most likely because its dependent job failed. has 2 failures:
  • Test uart has 2 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/uart-sim-vcs/cov_merge/merged.vdb/cov_merge.log

    • cov_report
      Log /nightly/current_run/scratch/master/uart-sim-vcs/cov_report/cov_report.log