CHIP Simulation Results

Friday August 29 2025 17:04:28 UTC

GitHub Revision: `751b8fb`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.049m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.049m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	3.807m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.181m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.912m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	22.158m	12.019ms	0	3	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	22.158m	12.019ms	0	3	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	22.158m	12.019ms	0	3	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	52.910s	10.160us	0	3	0.00
		chip_sw_example_manufacturer	5.333m		0	3	0.00
		chip_sw_example_concurrency	5.591m	5.446ms	3	3	100.00
		chip_sw_uart_smoketest_signed	16.604s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	12.920s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	13.200s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	13.200s		0	3	0.00
V1	xbar_smoke	xbar_smoke	45.300s	11.118us	0	100	0.00
V1		TOTAL			3	156	1.92
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	4.266m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	26.080m	12.019ms	0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	21.805m	12.019ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.309m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.882m		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.985m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.161m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	52.610s	10.120us	0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	52.610s	10.120us	0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.571m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.093m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.377m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.377m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	51.210s	10.140us	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	45.420s	10.280us	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	23.009m	12.018ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	16.978s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	16.176s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	43.560s	10.220us	0	3	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	8.826m	6.619ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	33.709m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	33.709m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	1.496m		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.947m	5.471ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.947m	5.471ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.505m	18.019ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.688m	4.949ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.999m	4.727ms	3	3	100.00
		chip_sw_aes_idle	5.713m	4.873ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.587m	3.634ms	3	3	100.00
		chip_sw_kmac_idle	5.678m	5.676ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	22.279m	12.019ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	21.938m	12.019ms	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	22.361m	12.018ms	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	21.941m	12.018ms	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	21.670s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.382s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.479s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.427s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.409m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	16.175s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	23.998s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	21.670s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.382s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.479s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.427s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.409m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	16.175s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	23.998s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	2.237m		0	3	0.00
		chip_sw_aes_enc_jitter_en	53.360s	10.240us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.031m	10.280us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.880s	10.160us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.220s	10.160us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	58.354s		0	3	0.00
		chip_sw_clkmgr_jitter	4.532m	4.274ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.627m	5.619ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.589s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	56.420s	10.180us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	44.110s	10.120us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	53.570s	10.100us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	59.470s	10.280us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	53.080s	10.320us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	16.658s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.227s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	16.923s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	37.044s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	12.208m	6.112ms	0	100	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.433m	4.492ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	6.947m	5.471ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	3.488m		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.433m	4.492ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.182m		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.598m		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	1.645m		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.623m		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.892m		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	12.208m	6.112ms	0	100	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	23.009m	12.018ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	36.909m	20.019ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.692m	9.826ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.665m	9.314ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.085m	4.125ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	12.208m	6.112ms	0	100	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.501s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	33.337s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	12.208m	6.112ms	0	100	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	20.786s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.665m	9.314ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	1.276m		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	20.308s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	30.948s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.588s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.990s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.265m		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	33.337s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.981m		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	9.748m	7.090ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.536m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	2.557m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	3.888m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	3.277m		0	3	0.00
		chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	11.707m	9.669ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	5.491m	4.505ms	0	3	0.00
		chip_sw_sram_ctrl_execution_main	1.055m		0	3	0.00
		chip_prim_tl_access	47.430s	10.140us	0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	21.670s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.382s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.479s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.427s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.409m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	16.175s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	23.998s		0	3	0.00
		chip_rv_dm_lc_disabled	43.560s	10.220us	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.458m	4.194ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	53.360s	10.240us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	6.018m	4.678ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.713m	4.873ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.188m	4.593ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.031m	10.280us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.587m	3.634ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.680m	4.383ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.470m	5.497ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	48.220s	10.160us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	11.707m	9.669ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	54.910s	10.220us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.509m	5.948ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.678m	5.676ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.677s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.677s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	25.854s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.753m	5.378ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	16.804s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	11.707m	9.669ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.880s	10.160us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	18.110s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	2.237m		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.999m	4.727ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.999m	4.727ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.999m	4.727ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.254m	6.184ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.491m	4.505ms	0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.491m	4.505ms	0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	15.936m	6.597ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	58.354s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	1.055m		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	12.208m	6.112ms	0	100	0.00
		chip_sw_data_integrity_escalation	2.377m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.254m	6.184ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.707m	9.669ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	15.936m	6.597ms	0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	6.891m	4.992ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.254m	6.184ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.707m	9.669ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	15.936m	6.597ms	0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	6.891m	4.992ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.743s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.981m		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.536m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	2.557m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	3.888m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	3.277m		0	3	0.00
		chip_sw_lc_ctrl_transition	2.021m		0	15	0.00
		chip_prim_tl_access	47.430s	10.140us	0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	47.430s	10.140us	0	3	0.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	2.342m		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	2.742m		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.227s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	2.237m		0	3	0.00
		chip_sw_aes_enc_jitter_en	53.360s	10.240us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.031m	10.280us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.880s	10.160us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.220s	10.160us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	58.354s		0	3	0.00
		chip_sw_clkmgr_jitter	4.532m	4.274ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	11.213m	5.889ms	0	3	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	11.213m	5.889ms	0	3	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.420m	5.196ms	3	3	100.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	6.137m	5.357ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	20.758m	12.019ms	0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	10.781m	5.740ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.598m	5.722ms	2	3	66.67
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	6.856m	4.273ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	6.891m	4.992ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	36.909m	20.019ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	36.909m	20.019ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	5.917m	5.001ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.134m	5.288ms	3	3	100.00
		chip_sw_clkmgr_smoketest	7.064m	5.140ms	3	3	100.00
		chip_sw_csrng_smoketest	4.855m	4.007ms	3	3	100.00
		chip_sw_gpio_smoketest	6.030m	5.082ms	3	3	100.00
		chip_sw_hmac_smoketest	6.303m	4.120ms	3	3	100.00
		chip_sw_kmac_smoketest	6.920m	5.349ms	3	3	100.00
		chip_sw_otbn_smoketest	7.348m	5.721ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.019m	4.701ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.410m	5.473ms	3	3	100.00
		chip_sw_rv_timer_smoketest	7.920m	5.699ms	3	3	100.00
		chip_sw_rstmgr_smoketest	6.628m	5.740ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	6.298m	5.041ms	3	3	100.00
		chip_sw_uart_smoketest	6.409m	5.123ms	0	3	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	15.985s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	16.604s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.266m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	15.538s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.369m	5.274ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.406m	3.852ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.626m	4.582ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.401m	4.043ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	2.090m		0	3	0.00
		chip_rv_dm_lc_disabled	43.560s	10.220us	0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	2.093m		0	3	0.00
		chip_sw_lc_walkthrough_prod	2.741m		0	3	0.00
		chip_sw_lc_walkthrough_prodend	1.943m		0	3	0.00
		chip_sw_lc_walkthrough_rma	2.216m		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	2.090m		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.508m		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.768m		0	3	0.00
		rom_volatile_raw_unlock	16.044s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	16.329s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	4.123m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.110m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	44.580s	10.180us	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	44.580s	10.180us	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	13.200s		0	3	0.00
		chip_same_csr_outstanding	12.550s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	13.200s		0	3	0.00
		chip_same_csr_outstanding	12.550s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	51.720s	12.030us	0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	52.470s	10.882us	0	100	0.00
		xbar_smoke_large_delays	52.180s	11.145us	0	100	0.00
		xbar_smoke_slow_rsp	53.610s	11.139us	0	100	0.00
		xbar_random_zero_delays	48.400s	10.904us	0	100	0.00
		xbar_random_large_delays	51.650s	11.235us	0	100	0.00
		xbar_random_slow_rsp	51.040s	11.036us	0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	46.330s	11.155us	0	100	0.00
		xbar_error_and_unmapped_addr	50.310s	12.307us	0	100	0.00
V2	xbar_error_cases	xbar_error_random	49.500s	10.892us	0	100	0.00
		xbar_error_and_unmapped_addr	50.310s	12.307us	0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device	52.380s	10.696us	0	100	0.00
		xbar_access_same_device_slow_rsp	49.010s	11.400us	0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	50.700s	10.877us	0	100	0.00
V2	xbar_stress_all	xbar_stress_all	52.950s	11.111us	0	100	0.00
		xbar_stress_all_with_error	43.010s	11.112us	0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	53.270s	11.124us	0	100	0.00
		xbar_stress_all_with_reset_error	50.890s	11.968us	0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	15.565s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	16.020s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	16.592s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	15.558s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	15.712s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	15.686s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	15.585s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	15.845s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.131s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.163s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.064s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.293s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.267s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.011s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	15.577s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	14.179s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	14.037s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	14.263s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.040s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.902s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.960s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.135s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.107s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.195s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.042s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.825s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.935s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.568s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.641s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.415s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.113s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.366s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.562s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	16.365s		0	3	0.00
		rom_e2e_asm_init_dev	16.506s		0	3	0.00
		rom_e2e_asm_init_prod	16.316s		0	3	0.00
		rom_e2e_asm_init_prod_end	15.473s		0	3	0.00
		rom_e2e_asm_init_rma	16.102s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	16.133s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	16.060s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	17.193s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	15.619s		0	3	0.00
V2		TOTAL			119	2429	4.90
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.033m	4.171ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	7.702m	5.806ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.020s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.928s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.148s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	33.379s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	12.208m	6.112ms	0	100	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.278m		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	8.869m	6.395ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	1.298m		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.980s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.020s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.928s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.148s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	15.854s		0	1	0.00
		rom_e2e_jtag_inject_dev	14.148s		0	1	0.00
		rom_e2e_jtag_inject_rma	14.203s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	16.609s		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	10.533m	6.616ms	0	3	0.00
		chip_sw_entropy_src_kat_test	5.288m	4.651ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.785m	4.859ms	3	3	100.00
		chip_plic_all_irqs_0	15.314m	7.210ms	3	3	100.00
		chip_plic_all_irqs_10	15.606m	7.823ms	3	3	100.00
		chip_sw_dma_inline_hashing	5.195m	5.375ms	0	3	0.00
		chip_sw_dma_abort	6.608m	4.027ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	16.492s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	16.567s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	16.280s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	16.864s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	16.172s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	16.097s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	15.047s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	16.337s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	14.055s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	16.121s		0	3	0.00
		chip_sw_entropy_src_smoketest	6.249m	4.952ms	3	3	100.00
		chip_sw_mbx_smoketest	6.129m	6.065ms	0	3	0.00
		TOTAL			143	2668	5.36

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
46.16	41.34	48.73	50.96	--	66.74	65.76	3.43

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .*.scr.vmem could not be opened for r mode has 1852 failures:
- Test chip_tl_errors has 30 failures.
  - 0.chip_tl_errors.18918456293363464478507079590786827716547097973022562497448102454855470719766
    Line 233, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_tl_errors.57580173296608632178559613666319045844591240756367157525251548955284355842555
    Line 233, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
- Test chip_prim_tl_access has 3 failures.
  - 0.chip_prim_tl_access.91210421140855651738735709361517692367800335674856102376762024796443445291672
    Line 233, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_prim_tl_access.54349974251402520209448473610522859457509387210380591999107241489425961135423
    Line 233, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_prim_tl_access/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_jtag_csr_rw has 3 failures.
  - 0.chip_jtag_csr_rw.72094474118506882946811064803438550098651911332471813542039930108466314548837
    Line 6263, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_jtag_csr_rw.21042730006940618228661872915249526817883241345444563026372222275477831354608
    Line 6263, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_jtag_mem_access has 3 failures.
  - 0.chip_jtag_mem_access.40584305810038171440215776702416123649881770495455426308013912879224600910419
    Line 6263, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_jtag_mem_access.8627721354869538274381613900004585614362360021721587667584683933331905057470
    Line 6263, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_rv_dm_lc_disabled has 3 failures.
  - 0.chip_rv_dm_lc_disabled.60795584059303957446372916531937387393978362600135381033969357252668024350825
    Line 220, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_lc_disabled.82637062044510127280990644701833044289907978513459364153226820986364956840031
    Line 220, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 19 more tests.

Job returned non-zero exit code has 455 failures:

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.71511490761109859784564690406395937305602041260378456823728115319023047466602
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 305.265s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.53668691936642002402949307265789224938839253847225427126180946771548317766506
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 1.744s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.88410365314168859168829645522832754329550540523361787766528273083269801416195
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.015s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.51596709692962011679225600102174595287005076944036432929017001450689792098214
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 6.772s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.90987360429211670673750591950947212670755774274964965577304608869492718602715
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 202.234s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.94344420510735166052755204073851445796297809583096532419813536482263714783543
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 2.784s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.78154829567857671415419791196809058865336076692354038745100769002657004124440
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 112.727s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.44422688270565258839239553556276154299831861427001403150941336917374263556252
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 2.782s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_uart_tx_rx has 5 failures.

0.chip_sw_uart_tx_rx.45834424865724700022721180560758046971932688579375990203384012230950537119308
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 230.729s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_uart_tx_rx.88735776645299397491853593883830385998008233749374128950694385559790010348584
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 1.802s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 3 more failures.

... and 131 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1168)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for alert_irq_seen has 104 failures:

Test chip_sw_all_escalation_resets has 100 failures.

0.chip_sw_all_escalation_resets.82929528109955252855969471989397211284516536363203408536850708703708264550417
Line 496, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 5979.283432 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1168)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for alert_irq_seen
  UVM_INFO @ 5979.283432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_all_escalation_resets.8948621605798032907503526576647162534548801895883827431063687523096763641434
Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 6955.089751 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1168)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for alert_irq_seen
  UVM_INFO @ 6955.089751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 98 more failures.

Test chip_sw_rstmgr_rst_cnsty_escalation has 3 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.41991217935320510624123890795234632703562446728356695648887373612464465661754
Line 476, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

  UVM_ERROR @ 6085.906664 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1168)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for alert_irq_seen
  UVM_INFO @ 6085.906664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_rst_cnsty_escalation.59955559633011058191168532319174581088765312493557784295640917276226557329069
Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

  UVM_ERROR @ 6615.515360 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1168)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for alert_irq_seen
  UVM_INFO @ 6615.515360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_otp_ctrl_escalation has 1 failures.

0.chip_sw_otp_ctrl_escalation.66747945827597031058057177652355379898824251933985565372712047729189314120472
Line 726, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log

  UVM_ERROR @ 6394.709495 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1168)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for alert_irq_seen
  UVM_INFO @ 6394.709495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 28 failures:

Test chip_sw_spi_device_pass_through has 3 failures.

0.chip_sw_spi_device_pass_through.110120672961036265582630608043182875733331285696100888672820860266275081333791
Line 656, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log

  UVM_ERROR @ 12026.799826 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.799826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_spi_device_pass_through.112472519247822251614287374501932965648210164515636928351833641020311850789017
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest/run.log

  UVM_ERROR @ 12018.590045 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.590045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_spi_device_pass_through_collision has 3 failures.

0.chip_sw_spi_device_pass_through_collision.96468255349927436099163193733740778471245599354573567591924339715635808021558
Line 676, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

  UVM_ERROR @ 12018.728927 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.728927 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_spi_device_pass_through_collision.30897631100046060572898716171767034971793204030581550841337606724001460791592
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log

  UVM_ERROR @ 12026.949301 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.949301 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_gpio has 3 failures.

0.chip_sw_gpio.82843349814156090935576715714845612098009226905739972152415914451862162378126
Line 556, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_gpio/latest/run.log

  UVM_ERROR @ 12018.549599 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.549599 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_gpio.20399405371349330250949242873466173724100073116062386511306659026845204731779
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_gpio/latest/run.log

  UVM_ERROR @ 12018.672657 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.672657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.28108465992487000307553457638956080936373986880992757396429134500861639836970
Line 636, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.619032 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.619032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.45959543574482052829543239970097901974353105436306330765304000827201320428834
Line 435, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.635932 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.635932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_soc_proxy_gpios has 3 failures.

0.chip_sw_soc_proxy_gpios.79964303452961456665013174698350758366527868046465270235264265868000626818359
Line 569, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log

  UVM_ERROR @ 12026.698451 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.698451 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_gpios.47996208165741920689089182091347367563515720803975917638305457034212739730150
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log

  UVM_ERROR @ 12018.500841 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.500841 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

... and 5 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.47160435350917987036191795522961917814204533340906039425375532271107546284299
    Line 430, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.65544690410280531494722025349996711698289099587599446420149696011369665854292
    Line 375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.32875538219406991426142876462777154802201127722581491454192571477485188834567
    Line 507, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.96015261250531161858281944036323198209552501025949639652283554051420705347433
    Line 419, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.93036862246576452273807441514704646275501440072128124211509693551902068971667
    Line 521, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.70787321012514919671297108348678118372923087011675402584225181490419425129967
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.72083369655477485619257672621556812253049542695525916599229376865265310487775
    Line 558, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.45005048041736022273415710980540180727982556193849573081848408893608145636857
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.28212290172820797972456631074653350673191530358254697625132368390676396386636
    Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.82003368298059616426074911553214092408134927785556179692423488720483248920496
    Line 374, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.71827425471888359120657136732140104462026546279126744482588114526813998135911
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.108065283373274129817692455566387789806501184896206008853285630109471081031785
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.75963141628925984872988211300495925037086870185947718808951520108804711598768
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.51652982425528152277262584978033464926133719666482219953719946017748184986574
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.90324150161461146684779834759453574126720650482939194206301924759502983230799
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.28916340642299402269115835800895011134188804774951671938525729288525206903097
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 8 failures:

Test chip_sw_clkmgr_off_aes_trans has 2 failures.

0.chip_sw_clkmgr_off_aes_trans.69154178851661271329320409477700098007790885395598778209111762964052930181836
Line 514, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.750580 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.750580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_aes_trans.36038840079659820535918571628395093891081032279825616037834817031313185778289
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.939128 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.939128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 2 failures.

0.chip_sw_clkmgr_off_hmac_trans.47950493253791609181217578774031236574594332595145783356775244835536777379293
Line 482, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.452461 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.452461 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_hmac_trans.21679660025632728821626330022417115580314571505272371026344755204716464703896
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.793096 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.793096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 2 failures.

0.chip_sw_clkmgr_off_kmac_trans.93633365957318948456733048922159088398338266045251512014812075467236031678796
Line 472, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12026.907902 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.907902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_kmac_trans.70119818614447052416245645851895035155833333822594741671945124428671881749949
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.432029 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.432029 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 2 failures.

1.chip_sw_clkmgr_off_otbn_trans.87125072514952395469778826496729103853687129864608165417328954814760950833629
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12027.013506 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12027.013506 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_otbn_trans.17080133075857711732052246921875802215446162465078567035805203074163829827309
Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.426682 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.426682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_example_rom has 3 failures.
  - 0.chip_sw_example_rom.41275196960585680378778520696062258922541614283654591795822311854729553672612
    Line 628, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_example_rom.36010729279959352560083204954235894095431593148539331623687293554510950005896
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:
- Test chip_sw_rstmgr_alert_info has 3 failures.
  - 0.chip_sw_rstmgr_alert_info.73257705544257381295751656303837325732539004679601023739342902253514485973243
    Line 813, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9314.139594 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9314.139594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rstmgr_alert_info.54392002414324387592028101962524046793694142050703171108510893492287658255631
    Line 646, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10767.817055 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10767.817055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:44)] CHECK-fail: Did not get reset in time! has 3 failures:
- Test chip_sw_soc_proxy_smoketest has 3 failures.
  - 0.chip_sw_soc_proxy_smoketest.67423691373235374477022431644774183073073835051449496461239403237289463065809
    Line 669, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 4869.577706 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:44)] CHECK-fail: Did not get reset in time!
  UVM_INFO @ 4869.577706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_smoketest.9745940852292567719152710419880001233671955654200496508444831406212543698975
    Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 5889.403928 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:44)] CHECK-fail: Did not get reset in time!
  UVM_INFO @ 5889.403928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
- Test chip_sw_soc_proxy_external_wakeup has 3 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.103924222168559871592647353310937424312172993764546694908876455782258521132805
    Line 670, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3816.562552 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3816.562552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_external_wakeup.15213825609645231972125459297457157216001500438722920584746748008881067759301
    Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5356.723101 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5356.723101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.57976209706288860618870308719985269284277928821499192575163088778026875534631
    Line 599, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3394.951317 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3394.951317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.61433157676032532731409472544418550866705185492215388094631692676416883509249
    Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4221.569055 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4221.569055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.81025217722572611483451712956617610442252944250512063713745312835007606270390
    Line 613, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4714.792465 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4714.792465 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.54779726505669272014995117857889334016360428477499244674359120266911225176459
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5739.739832 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5739.739832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.31461656576217004664696761470893766539478257882677911268923275065158133707446
    Line 539, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.24039702584783004109960869179110212907253560778403997611763943825241440456224
    Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 3 failures:
- Test chip_sw_rom_ctrl_integrity_check has 3 failures.
  - 0.chip_sw_rom_ctrl_integrity_check.65480572974475345563981837103880809801320446522241221158575397689125484026722
    Line 533, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest/run.log
```
  UVM_ERROR @ 4504.794900 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 4504.794900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rom_ctrl_integrity_check.21536745470161343692522138477866404479045517484339809212513030142412037174872
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest/run.log
```
  UVM_ERROR @ 3672.059230 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3672.059230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:* = ErrorError has 3 failures:
- Test chip_sw_sram_ctrl_scrambled_access has 3 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access.103081523555536655578068427506483055931160460913619698543571929222832128627842
    Line 469, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 7030.086200 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 7030.086200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_sram_ctrl_scrambled_access.21442886467546818524414382946275748436178777330179613926370582105295870608822
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 7888.588837 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 7888.588837 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_inline_hashing_sim_dv(sw/device/tests/dma_inline_hashing.c:195)] DIF-fail: dif_dma_get_digest_length(kShaMode, &digest_len) returns * has 3 failures:
- Test chip_sw_dma_inline_hashing has 3 failures.
  - 0.chip_sw_dma_inline_hashing.17071110146473544541176344108954414073853014932649002704169973894827304845272
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_inline_hashing/latest/run.log
```
  UVM_ERROR @ 5374.583804 us: (sw_logger_if.sv:526) [dma_inline_hashing_sim_dv(sw/device/tests/dma_inline_hashing.c:195)] DIF-fail: dif_dma_get_digest_length(kShaMode, &digest_len) returns 3
  UVM_INFO @ 5374.583804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_dma_inline_hashing.43062632741873241360214228564347826286001406536244370467686685023728519866268
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_inline_hashing/latest/run.log
```
  UVM_ERROR @ 4931.231431 us: (sw_logger_if.sv:526) [dma_inline_hashing_sim_dv(sw/device/tests/dma_inline_hashing.c:195)] DIF-fail: dif_dma_get_digest_length(kShaMode, &digest_len) returns 3
  UVM_INFO @ 4931.231431 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 3 failures:
- Test chip_sw_dma_abort has 3 failures.
  - 0.chip_sw_dma_abort.102327909638809557748950176171276373805003031544831568616115663891038655628860
    Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_ERROR @ 4026.878552 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
  UVM_INFO @ 4026.878552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_dma_abort.33546699595484187019461191253185373480624250348257310699784615284057140081242
    Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log
```
  UVM_ERROR @ 3970.300810 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
  UVM_INFO @ 3970.300810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [mbx_smoketest_sim_dv(sw/device/tests/mbx_smoketest.c:372)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 3 failures:
- Test chip_sw_mbx_smoketest has 3 failures.
  - 0.chip_sw_mbx_smoketest.62596522724236972654479170351677456781705049637343690398064641498288509377215
    Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_mbx_smoketest/latest/run.log
```
  UVM_ERROR @ 6065.351040 us: (sw_logger_if.sv:526) [mbx_smoketest_sim_dv(sw/device/tests/mbx_smoketest.c:372)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for kSoftwareBarrier == 1
  UVM_INFO @ 6065.351040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_mbx_smoketest.18636553698414364715517430424688006767295382026050890264804502435583195390000
    Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_mbx_smoketest/latest/run.log
```
  UVM_ERROR @ 4477.414380 us: (sw_logger_if.sv:526) [mbx_smoketest_sim_dv(sw/device/tests/mbx_smoketest.c:372)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for kSoftwareBarrier == 1
  UVM_INFO @ 4477.414380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [uart_smoketest_sim_dv(sw/device/tests/uart_smoketest.c:44)] CHECK-fail: receive_byte == kSendData[i] has 3 failures:
- Test chip_sw_uart_smoketest has 3 failures.
  - 0.chip_sw_uart_smoketest.76386259599968074100105789697296522726442518740146911444216174612985172676984
    Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest/latest/run.log
```
  UVM_ERROR @ 4995.159375 us: (sw_logger_if.sv:526) [uart_smoketest_sim_dv(sw/device/tests/uart_smoketest.c:44)] CHECK-fail: receive_byte == kSendData[i]
  UVM_INFO @ 4995.159375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_uart_smoketest.105042372861214111035059473537430777979234161303150319208101513616951209227184
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_smoketest/latest/run.log
```
  UVM_ERROR @ 3789.526389 us: (sw_logger_if.sv:526) [uart_smoketest_sim_dv(sw/device/tests/uart_smoketest.c:44)] CHECK-fail: receive_byte == kSendData[i]
  UVM_INFO @ 3789.526389 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 1 failures:
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_otbn_trans.88411753596055712186853281561499991979852528185349086179674127750796779774441
    Line 482, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
  UVM_ERROR @ 12018.380562 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.380562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 2.chip_sw_rv_core_ibex_rnd.84234507798943595707928595343614301939638307039676791046080834538139894487660
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 5722.023028 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 5722.023028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 1 failures:
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 2.chip_sw_clkmgr_off_aes_trans.64486899825626654881174668048265566897183198189709142982300226372216330776300
    Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
  UVM_ERROR @ 12018.544440 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.544440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```