AES/MASKED Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: `6181a2d`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	102.949us	1	1	100.00
V1	smoke	aes_smoke	32.000s	2.330ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	101.272us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	85.753us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	188.343us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	265.164us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	70.876us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	85.753us	20	20	100.00
		aes_csr_aliasing	5.000s	265.164us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	32.000s	2.330ms	50	50	100.00
		aes_config_error	12.000s	596.000us	50	50	100.00
		aes_stress	15.000s	282.526us	50	50	100.00
V2	key_length	aes_smoke	32.000s	2.330ms	50	50	100.00
		aes_config_error	12.000s	596.000us	50	50	100.00
		aes_stress	15.000s	282.526us	50	50	100.00
V2	back2back	aes_stress	15.000s	282.526us	50	50	100.00
		aes_b2b	29.000s	879.031us	50	50	100.00
V2	backpressure	aes_stress	15.000s	282.526us	50	50	100.00
V2	multi_message	aes_smoke	32.000s	2.330ms	50	50	100.00
		aes_config_error	12.000s	596.000us	50	50	100.00
		aes_stress	15.000s	282.526us	50	50	100.00
		aes_alert_reset	11.000s	499.753us	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	407.995us	50	50	100.00
		aes_config_error	12.000s	596.000us	50	50	100.00
		aes_alert_reset	11.000s	499.753us	50	50	100.00
V2	trigger_clear_test	aes_clear	21.000s	1.886ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	309.168us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	499.753us	50	50	100.00
V2	stress	aes_stress	15.000s	282.526us	50	50	100.00
V2	sideload	aes_stress	15.000s	282.526us	50	50	100.00
		aes_sideload	17.000s	647.919us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	277.503us	50	50	100.00
V2	stress_all	aes_stress_all	1.200m	1.159ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	109.451us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	125.530us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	125.530us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	101.272us	5	5	100.00
		aes_csr_rw	4.000s	85.753us	20	20	100.00
		aes_csr_aliasing	5.000s	265.164us	5	5	100.00
		aes_same_csr_outstanding	4.000s	250.960us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	101.272us	5	5	100.00
		aes_csr_rw	4.000s	85.753us	20	20	100.00
		aes_csr_aliasing	5.000s	265.164us	5	5	100.00
		aes_same_csr_outstanding	4.000s	250.960us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	45.000s	7.898ms	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_cipher_fi	56.000s	10.142ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	72.094us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	72.094us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	72.094us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	72.094us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	172.219us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	1.782ms	5	5	100.00
		aes_tl_intg_err	6.000s	1.655ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.655ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	499.753us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	72.094us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	32.000s	2.330ms	50	50	100.00
		aes_stress	15.000s	282.526us	50	50	100.00
		aes_alert_reset	11.000s	499.753us	50	50	100.00
		aes_core_fi	1.000m	10.015ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	72.094us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	207.591us	50	50	100.00
		aes_stress	15.000s	282.526us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	282.526us	50	50	100.00
		aes_sideload	17.000s	647.919us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	207.591us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	207.591us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	207.591us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	207.591us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	207.591us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	282.526us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	282.526us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	262.702us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_cipher_fi	56.000s	10.142ms	344	350	98.29
		aes_ctr_fi	7.000s	366.822us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	262.702us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_cipher_fi	56.000s	10.142ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	56.000s	10.142ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	262.702us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_ctr_fi	7.000s	366.822us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_cipher_fi	56.000s	10.142ms	344	350	98.29
		aes_ctr_fi	7.000s	366.822us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	499.753us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_cipher_fi	56.000s	10.142ms	344	350	98.29
		aes_ctr_fi	7.000s	366.822us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_cipher_fi	56.000s	10.142ms	344	350	98.29
		aes_ctr_fi	7.000s	366.822us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_ctr_fi	7.000s	366.822us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	262.702us	50	50	100.00
		aes_control_fi	29.000s	10.007ms	286	300	95.33
		aes_cipher_fi	56.000s	10.142ms	344	350	98.29
V2S		TOTAL			962	985	97.66
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	42.000s	739.446us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1569	1602	97.94

Failure Buckets

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.52372859785212809846670552761978328738016007447321836838555863155440105568238
Line 195, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9608510135 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9608510135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.65879308444403076913366774147411687341403040706626988473544522450597263020149
Line 215, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  74650390 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  74650390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 21.aes_control_fi.17847978620222227000180282100477112997255469443323655862828201503110483078245
    Line 147, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10048166349 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10048166349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 94.aes_control_fi.22462203318092552048422156541529337703491721230076594839617534374641293703975
    Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/94.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018323775 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018323775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
Job timed out after * minutes has 7 failures:
- Test aes_control_fi has 7 failures.
  - 47.aes_control_fi.66316733985874023969572062518074055742455285833480612052050412999091009325823
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/47.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 73.aes_control_fi.55861773963332880588928333269845180894120383392888170281364300973468781736058
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/73.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 20.aes_cipher_fi.110555825629558300363352028855544400672913869621367121450768844283216723781667
    Line 136, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10029506297 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029506297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_cipher_fi.37558817353772770173954627056624604347023316478434190994668837563207255700093
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10142222211 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10142222211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:946) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 5.aes_stress_all_with_rand_reset.83410998957864582202871552884599024356963586225378034878847467777687671859512
    Line 155, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112610891 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112610891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.37329218749186891117300512576261904649803551979490524450539940632266362469837
    Line 151, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 125086858 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 125086858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 12.aes_core_fi.55047107373800323260669083125564319323060151296194134112206216204021533410346
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015487372 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015487372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.aes_core_fi.55131606225353040817530149655381730583941478095677410416527822396576890145099
    Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009347765 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009347765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.7631676928825389750203181415493512950233215895676027948886752588560453254373
    Line 438, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1894842478 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1894842478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 59.aes_core_fi.102441020249274867356685881823458397975262105957926028728697438285748601202145
    Line 126, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/59.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024291537 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x4a2c1c84, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
  UVM_INFO @ 10024291537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.log