EDN Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.270s 51.101us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.940s 34.887us 5 5 100.00
V1 csr_rw edn_csr_rw 0.970s 11.856us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.450s 995.843us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 0.990s 16.778us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.710s 59.367us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.970s 11.856us 20 20 100.00
edn_csr_aliasing 0.990s 16.778us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 3.120s 300.626us 300 300 100.00
V2 csrng_commands edn_genbits 3.120s 300.626us 300 300 100.00
V2 genbits edn_genbits 3.120s 300.626us 300 300 100.00
V2 interrupts edn_intr 1.530s 24.403us 50 50 100.00
V2 alerts edn_alert 1.690s 236.002us 200 200 100.00
V2 errs edn_err 1.580s 48.535us 100 100 100.00
V2 disable edn_disable 1.220s 35.258us 50 50 100.00
edn_disable_auto_req_mode 1.600s 40.955us 50 50 100.00
V2 stress_all edn_stress_all 5.750s 393.765us 50 50 100.00
V2 intr_test edn_intr_test 1.100s 14.114us 50 50 100.00
V2 alert_test edn_alert_test 2.010s 333.135us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.080s 535.050us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.080s 535.050us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.940s 34.887us 5 5 100.00
edn_csr_rw 0.970s 11.856us 20 20 100.00
edn_csr_aliasing 0.990s 16.778us 5 5 100.00
edn_same_csr_outstanding 1.410s 36.033us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.940s 34.887us 5 5 100.00
edn_csr_rw 0.970s 11.856us 20 20 100.00
edn_csr_aliasing 0.990s 16.778us 5 5 100.00
edn_same_csr_outstanding 1.410s 36.033us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.490s 1.111ms 5 5 100.00
edn_tl_intg_err 4.390s 357.059us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.290s 27.890us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.690s 236.002us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.490s 1.111ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.490s 1.111ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.490s 1.111ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.490s 1.111ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.690s 236.002us 200 200 100.00
edn_sec_cm 7.490s 1.111ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.690s 236.002us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.390s 357.059us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.756m 100.670ms 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 1109 1130 98.14

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.81 98.87 94.23 97.07 91.28 96.33 99.78 93.13

Failure Buckets