HMAC Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.050s	4.284ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.300s	84.399us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.230s	32.987us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.880s	611.631us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.540s	1.586ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	3.610s	38.013us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.230s	32.987us	20	20	100.00
		hmac_csr_aliasing	8.540s	1.586ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.188m	10.560ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.657m	12.007ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.704m	49.348ms	30	30	100.00
		hmac_test_sha384_vectors	8.971m	14.261ms	75	75	100.00
		hmac_test_sha512_vectors	9.712m	14.106ms	75	75	100.00
		hmac_test_hmac256_vectors	14.330s	5.505ms	50	50	100.00
		hmac_test_hmac384_vectors	17.130s	777.341us	60	60	100.00
		hmac_test_hmac512_vectors	20.650s	3.034ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	31.840s	2.431ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	27.658m	8.382ms	10	10	100.00
V2	error	hmac_error	1.338m	33.066ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.844m	28.147ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.050s	4.284ms	10	10	100.00
		hmac_long_msg	1.188m	10.560ms	10	10	100.00
		hmac_back_pressure	1.657m	12.007ms	25	25	100.00
		hmac_datapath_stress	27.658m	8.382ms	10	10	100.00
		hmac_burst_wr	31.840s	2.431ms	50	50	100.00
		hmac_stress_all	34.971m	22.039ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.050s	4.284ms	10	10	100.00
		hmac_long_msg	1.188m	10.560ms	10	10	100.00
		hmac_back_pressure	1.657m	12.007ms	25	25	100.00
		hmac_datapath_stress	27.658m	8.382ms	10	10	100.00
		hmac_wipe_secret	1.844m	28.147ms	10	10	100.00
		hmac_test_sha256_vectors	4.704m	49.348ms	30	30	100.00
		hmac_test_sha384_vectors	8.971m	14.261ms	75	75	100.00
		hmac_test_sha512_vectors	9.712m	14.106ms	75	75	100.00
		hmac_test_hmac256_vectors	14.330s	5.505ms	50	50	100.00
		hmac_test_hmac384_vectors	17.130s	777.341us	60	60	100.00
		hmac_test_hmac512_vectors	20.650s	3.034ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.050s	4.284ms	10	10	100.00
		hmac_long_msg	1.188m	10.560ms	10	10	100.00
		hmac_back_pressure	1.657m	12.007ms	25	25	100.00
		hmac_datapath_stress	27.658m	8.382ms	10	10	100.00
		hmac_burst_wr	31.840s	2.431ms	50	50	100.00
		hmac_error	1.338m	33.066ms	10	10	100.00
		hmac_wipe_secret	1.844m	28.147ms	10	10	100.00
		hmac_test_sha256_vectors	4.704m	49.348ms	30	30	100.00
		hmac_test_sha384_vectors	8.971m	14.261ms	75	75	100.00
		hmac_test_sha512_vectors	9.712m	14.106ms	75	75	100.00
		hmac_test_hmac256_vectors	14.330s	5.505ms	50	50	100.00
		hmac_test_hmac384_vectors	17.130s	777.341us	60	60	100.00
		hmac_test_hmac512_vectors	20.650s	3.034ms	75	75	100.00
		hmac_stress_all	34.971m	22.039ms	50	50	100.00
V2	stress_all	hmac_stress_all	34.971m	22.039ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.880s	23.632us	50	50	100.00
V2	intr_test	hmac_intr_test	0.910s	19.827us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.630s	211.529us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.630s	211.529us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.300s	84.399us	5	5	100.00
		hmac_csr_rw	1.230s	32.987us	20	20	100.00
		hmac_csr_aliasing	8.540s	1.586ms	5	5	100.00
		hmac_same_csr_outstanding	2.700s	247.121us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.300s	84.399us	5	5	100.00
		hmac_csr_rw	1.230s	32.987us	20	20	100.00
		hmac_csr_aliasing	8.540s	1.586ms	5	5	100.00
		hmac_same_csr_outstanding	2.700s	247.121us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.180s	46.754us	5	5	100.00
		hmac_tl_intg_err	4.850s	286.916us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.850s	286.916us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.050s	4.284ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.760s	136.257us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	18.650m	435.123ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.000s	92.744us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.98	99.95	96.80	100.00	100.00	99.83	100.00	47.30