I2C Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: `6181a2d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.352m	1.905ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	41.160s	16.280ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.070s	147.591us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.090s	75.533us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.260s	441.584us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.260s	120.952us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.530s	54.445us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.090s	75.533us	20	20	100.00
		i2c_csr_aliasing	2.260s	120.952us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	6.930s	393.520us	4	50	8.00
V2	host_stress_all	i2c_host_stress_all	26.457m	40.906ms	11	50	22.00
V2	host_maxperf	i2c_host_perf	16.048m	50.293ms	49	50	98.00
V2	host_override	i2c_host_override	0.990s	31.680us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.424m	21.436ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.344m	2.647ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.630s	146.754us	50	50	100.00
		i2c_host_fifo_fmt_empty	21.470s	427.053us	50	50	100.00
		i2c_host_fifo_reset_rx	10.050s	822.401us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.524m	4.075ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	47.420s	2.311ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.140s	566.411us	15	50	30.00
V2	target_glitch	i2c_target_glitch	3.520s	1.582ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	30.560m	65.491ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	7.450s	1.904ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.098m	1.742ms	50	50	100.00
		i2c_target_intr_smoke	8.760s	18.198ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.100s	386.397us	50	50	100.00
		i2c_target_fifo_reset_tx	2.240s	938.777us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	13.893m	60.453ms	50	50	100.00
		i2c_target_stress_rd	1.098m	1.742ms	50	50	100.00
		i2c_target_intr_stress_wr	8.839m	37.327ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	9.390s	3.352ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.887m	5.217ms	40	50	80.00
V2	bad_address	i2c_target_bad_addr	7.280s	20.000ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	41.770s	10.005ms	20	50	40.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.590s	956.462us	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.320s	204.111us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	16.048m	50.293ms	49	50	98.00
		i2c_host_perf_precise	3.683m	23.271ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	47.420s	2.311ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	21.780s	1.383ms	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.190s	637.993us	50	50	100.00
		i2c_target_nack_acqfull_addr	3.920s	4.346ms	50	50	100.00
		i2c_target_nack_txstretch	1.950s	148.199us	36	50	72.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	20.760s	2.675ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.490s	600.757us	50	50	100.00
V2	alert_test	i2c_alert_test	0.940s	17.904us	50	50	100.00
V2	intr_test	i2c_intr_test	0.980s	29.642us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.710s	111.540us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.710s	111.540us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.070s	147.591us	5	5	100.00
		i2c_csr_rw	1.090s	75.533us	20	20	100.00
		i2c_csr_aliasing	2.260s	120.952us	5	5	100.00
		i2c_same_csr_outstanding	1.430s	50.434us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.070s	147.591us	5	5	100.00
		i2c_csr_rw	1.090s	75.533us	20	20	100.00
		i2c_csr_aliasing	2.260s	120.952us	5	5	100.00
		i2c_same_csr_outstanding	1.430s	50.434us	19	20	95.00
V2		TOTAL			1605	1792	89.56
V2S	tl_intg_err	i2c_tl_intg_err	2.670s	253.061us	20	20	100.00
		i2c_sec_cm	1.320s	74.106us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.670s	253.061us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	53.140s	3.983ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.590s	269.849us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	33.650s	1.008ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1785	2042	87.41

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.45	97.31	89.25	74.17	48.21	93.97	98.52	89.75

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 90 failures:

Test i2c_host_mode_toggle has 16 failures.

0.i2c_host_mode_toggle.42927887245511751229895319894839785661638847344596624895734690961825521019707
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  97617373 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  97617373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_mode_toggle.42081266902805658806174870453754811472095892494525346619625295927579472957181
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  28246824 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  28246824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test i2c_host_error_intr has 46 failures.

1.i2c_host_error_intr.105045385543438381593604698609292963532865189912750277251715293645036972514175
Line 96, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  16101853 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  16101853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_error_intr.95331526214059129092054725468094451291575312071691510253474946491140898070083
Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  87305373 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  87305373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 44 more failures.

Test i2c_host_stress_all has 25 failures.

2.i2c_host_stress_all.21188437726558936990436933550925326333691338287723339226090979710292163941319
Line 142, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 22230088275 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 22230088275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stress_all.76869220348323085470018029585332965422376779802257993551539062779770251910310
Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 3364437539 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 3364437539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Test i2c_target_stress_all_with_rand_reset has 3 failures.

3.i2c_target_stress_all_with_rand_reset.102988700919015437387236135155157612933151960341249887721243964143062241532302
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 223187393 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 223187393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.i2c_target_stress_all_with_rand_reset.44894771974140287452615737441100824524997731264003912173358131889470576396042
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  42746923 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  42746923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
- Test i2c_target_hrst has 30 failures.
  - 2.i2c_target_hrst.46526189101876414440674224729229310937768200025129515347688452629015662939128
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10704182807 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10704182807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_hrst.75591821479760255279819408792233380666415550423446477309464777926610351052978
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10383932646 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10383932646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
- Test i2c_target_unexp_stop has 27 failures.
  - 2.i2c_target_unexp_stop.4380705915150308387540751069496293470705863731231469448405936919051606453852
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 154772229 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 200 [0xc8])
  UVM_INFO @ 154772229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.77165009910567516275925623153701463277203004031385152003584756751525485036338
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  93882312 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 21 [0x15])
  UVM_INFO @  93882312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 25 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 17 failures:

Test i2c_host_stress_all has 11 failures.

0.i2c_host_stress_all.13509197013581268923812013707079101020030731570217848529209317697293352260646
Line 132, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 26973721640 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4393542

1.i2c_host_stress_all.1764049893100573499483095288438951636162216572028679225956866700743768219231
Line 153, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 91538382155 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5399288

... and 9 more failures.

Test i2c_host_mode_toggle has 6 failures.

9.i2c_host_mode_toggle.33093878447021125711196613193767783508340063596588987314006198314409593529088
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 133063891 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @8527

27.i2c_host_mode_toggle.45998399202301009769697801199100050688389335555324379947824821951397438841008
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 137008022 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @36631

... and 4 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 1.i2c_target_unexp_stop.18433583895886888639898542034364279695914360271617155936426470445606119174533
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1252300429 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1252300429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.105908618251719527661848943289250054493665842415571657515078730897998537520310
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 115806632 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 115806632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.104861172169527213847147780755616327955277159662644174493297379032502776671162
Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11462765680 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11462765680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.70413117861579776872284615706129245908894198234144503425494289599740687410854
Line 117, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1379112849 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1379112849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

1.i2c_target_stress_all_with_rand_reset.108702103786803569118389630965861666829653850959070005072396733245439887008880
Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 479576562 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 479576562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.99972438247472111159158517158413689932112847159069663498046192422294796801969
Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1007590164 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1007590164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
- Test i2c_target_nack_txstretch has 14 failures.
  - 4.i2c_target_nack_txstretch.21166011543503138569670011810877924101833983258440448398047081820365521681759
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 997103007 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 997103007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_nack_txstretch.44030905738223425327155028052656563800574521718987373720412827348508325860340
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 938217528 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 938217528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 12 failures.

6.i2c_host_mode_toggle.16958390614294319576526429139971768297858421273707649250954902608840789620621
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  46579952 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

17.i2c_host_mode_toggle.100561078491933096953210206877536380677121445886215187236824367832971425388722
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 467579154 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

Test i2c_host_perf has 1 failures.

10.i2c_host_perf.36790625832581778830633596715243999104731861801014621946845433246351708558737
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_host_perf/latest/run.log

  UVM_ERROR @ 3837140853 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 10 failures:
- Test i2c_target_stretch has 10 failures.
  - 10.i2c_target_stretch.86372042663600762644330064113905249202073952474879522844904497378935340678172
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011230452 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011230452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.i2c_target_stretch.9359405915104471551145898695431046251728637284499149879776705473416183342720
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/15.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011697587 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011697587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:

Test i2c_target_unexp_stop has 7 failures.

0.i2c_target_unexp_stop.72167123776429502300355171494434778913974252469925315741901071512691642377579
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 168692536 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 168692536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_unexp_stop.74451446660110922193056046432352070274954890580549923444049073718088506800764
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 326762246 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 326762246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 24.i2c_target_tx_stretch_ctrl.17130130590626455541018661788791072218179923586440595152568790370869730924813
    Line 132, in log /nightly/current_run/scratch/master/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 39.i2c_target_tx_stretch_ctrl.9828615192084901540486166085436662954499197578333030160483677972987134729133
    Line 126, in log /nightly/current_run/scratch/master/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 39.i2c_target_fifo_watermarks_tx.13476106124970993019118418110527348698647308300320769442996060194888082018575
    Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all has 2 failures.
  - 2.i2c_target_stress_all.37140065196679422942510491976007334871382833481707938598581725834360580652598
    Line 111, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 86560796539 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 86560796539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_stress_all.17617960934081509152401489274879803538676112175572407009148800635663164331037
    Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 27970745443 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 27970745443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_intr_stress_wr has 1 failures.
  - 46.i2c_target_intr_stress_wr.84247311575701520304439897384337533810395520836731656520599860300074185569766
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 37326584494 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 37326584494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.87688431299675597175215464361194384604064949177525033219322613842425634489867
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 1792117909 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1792117909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.69352012743174607903919669518140444672793991530321859303506421701981725032875
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 1581647595 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1581647595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:849) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 0.i2c_target_stress_all_with_rand_reset.113866303983585731270057281670091563869400078460905614375622739958230622305024
    Line 108, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 778178101 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 778178101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.i2c_target_stress_all_with_rand_reset.38466851027491339820372155746920521605023200639664026956924739724397163917949
    Line 142, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8151923409 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8151923409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

27.i2c_host_stress_all.48581587543193001356731402698275619982340979213498183935691682659595809703101
Line 200, in log /nightly/current_run/scratch/master/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 12022168683 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3857150

39.i2c_host_stress_all.21833075970185836709090331765873424127646634689250862225501252379311145518181
Line 165, in log /nightly/current_run/scratch/master/i2c-sim-vcs/39.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 81523196934 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5351876

UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 14.i2c_same_csr_outstanding.88956758763133146499559162634392223009537368112428628500962895010188590210449
    Line 74, in log /nightly/current_run/scratch/master/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  48303926 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  48303926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 28.i2c_host_mode_toggle.106084009377297195661154828551627017558146553793245213515569851117861325357176
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/28.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 39.i2c_target_bad_addr.24702318756824158490559566994021944597753332265511503263546050435922035393849
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/39.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 43.i2c_host_stress_all.99674561121963285084499620744747126777141245997435269096740368322689475757746
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```