KEYMGR Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: `6181a2d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	56.960s	34.493ms	50	50	100.00
V1	random	keymgr_random	19.730s	1.881ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.440s	115.999us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.620s	34.513us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.950s	259.739us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.340s	1.490ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.700s	473.708us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.620s	34.513us	20	20	100.00
		keymgr_csr_aliasing	10.340s	1.490ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.395m	4.422ms	50	50	100.00
V2	sideload	keymgr_sideload	21.930s	9.522ms	50	50	100.00
		keymgr_sideload_kmac	24.180s	1.365ms	50	50	100.00
		keymgr_sideload_aes	26.460s	1.494ms	49	50	98.00
		keymgr_sideload_otbn	42.210s	14.054ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	23.290s	5.104ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	58.940s	2.731ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.010s	229.893us	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.146m	12.030ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	58.320s	4.821ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	20.320s	1.093ms	49	50	98.00
V2	stress_all	keymgr_stress_all	2.410m	29.782ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.090s	13.161us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.400s	27.582us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.810s	826.463us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.810s	826.463us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.440s	115.999us	5	5	100.00
		keymgr_csr_rw	1.620s	34.513us	20	20	100.00
		keymgr_csr_aliasing	10.340s	1.490ms	5	5	100.00
		keymgr_same_csr_outstanding	3.440s	298.044us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.440s	115.999us	5	5	100.00
		keymgr_csr_rw	1.620s	34.513us	20	20	100.00
		keymgr_csr_aliasing	10.340s	1.490ms	5	5	100.00
		keymgr_same_csr_outstanding	3.440s	298.044us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
		keymgr_tl_intg_err	6.380s	366.346us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.850s	238.485us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.850s	238.485us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.850s	238.485us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.850s	238.485us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.870s	670.954us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.380s	366.346us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.850s	238.485us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.395m	4.422ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	19.730s	1.881ms	50	50	100.00
		keymgr_csr_rw	1.620s	34.513us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	19.730s	1.881ms	50	50	100.00
		keymgr_csr_rw	1.620s	34.513us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	19.730s	1.881ms	50	50	100.00
		keymgr_csr_rw	1.620s	34.513us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	58.940s	2.731ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	58.320s	4.821ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	58.320s	4.821ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	19.730s	1.881ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.980s	2.123ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	57.040s	3.242ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	58.940s	2.731ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	57.040s	3.242ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	57.040s	3.242ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	57.040s	3.242ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.610s	1.563ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	57.040s	3.242ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.030s	12.076ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1083	1110	97.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.80	99.13	98.18	98.53	100.00	99.01	98.63	91.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 7.keymgr_stress_all_with_rand_reset.55026749171231790307578664967893017837568001629413973262012732240851905021417
    Line 245, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 262651174 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 262651174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.keymgr_stress_all_with_rand_reset.31515218036283945604673702112095608009469425524304662555344992055186859288836
    Line 155, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 119780915 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 119780915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_kmac_rsp_err has 2 failures.

1.keymgr_kmac_rsp_err.91941508605050103507658536150993078466875438057706100433873434691477529733287
Line 599, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 134417740 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 134417740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.keymgr_kmac_rsp_err.96467706154143430273117952705652742972223569274676882340467003744778893546861
Line 659, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 158824996 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 158824996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all_with_rand_reset has 1 failures.

17.keymgr_stress_all_with_rand_reset.58442063412678056447546166405760387346705796563044740127446222068792064438696
Line 211, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 106926970 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 106926970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sync_async_fault_cross has 1 failures.

31.keymgr_sync_async_fault_cross.102445471666857908869200525462525504310606891043176715096526981279250682200656
Line 136, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest/run.log

  UVM_ERROR @  14275212 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  14275212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_aes has 1 failures.

49.keymgr_sideload_aes.28751804421134193342424687456368167504125764862539744796740122413840288944735
Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/49.keymgr_sideload_aes/latest/run.log

  UVM_ERROR @   9785878 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   9785878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:849) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 3.keymgr_stress_all_with_rand_reset.27434267391967316759780871598470823304409974839049416935518741216730807062601
    Line 155, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 487389138 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 487389138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 42.keymgr_stress_all_with_rand_reset.60656669399290718016595061275184069199543865144900621246514539497710299945428
    Line 150, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 706795785 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 706795785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 6.keymgr_stress_all.23036720047277735713033209196577443130205044649448596098246840281299650923117
    Line 513, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 351514458 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1269366119 [0x4ba8fd67] vs 1269366119 [0x4ba8fd67]) reg name: keymgr_reg_block.sw_share1_output_1
  UVM_INFO @ 351514458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 9.keymgr_stress_all.20285153196563857884629940935963036234948190407767552214284152579552913936878
    Line 931, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1335170529 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 1335170529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 24.keymgr_lc_disable.9104101241258475973407601442368811660814922395561249769369169430892737144808
    Line 155, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  85345850 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3656242503 [0xd9edd547] vs 3656242503 [0xd9edd547]) reg name: keymgr_reg_block.sw_share0_output_1
  UVM_INFO @  85345850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```