KEYMGR_DPE Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.537m	20.555ms	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.450s	35.976us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.610s	41.989us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	9.180s	3.567ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.290s	124.266us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.920s	41.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.610s	41.989us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.290s	124.266us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	1.160s	20.871us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.450s	27.495us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	4.380s	653.381us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	4.380s	653.381us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.450s	35.976us	5	5	100.00
		keymgr_dpe_csr_rw	1.610s	41.989us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.290s	124.266us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.570s	391.132us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.450s	35.976us	5	5	100.00
		keymgr_dpe_csr_rw	1.610s	41.989us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.290s	124.266us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.570s	391.132us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	15.950s	690.029us	5	5	100.00
		keymgr_dpe_tl_intg_err	7.410s	840.236us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.310s	121.790us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.310s	121.790us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.310s	121.790us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.310s	121.790us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.620s	628.687us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	15.950s	690.029us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	15.950s	690.029us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			309	310	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.69	97.60	90.15	63.14	75.68	94.71	98.57	16.96

Failure Buckets

• UVM_ERROR (keymgr_dpe_scoreboard.sv:583) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:
  • Test keymgr_dpe_smoke has 1 failures.

    • 30.keymgr_dpe_smoke.61102068887725389754849475420635789410699750149335532537666536616617262397848
      Line 2546, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/30.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 556455151 ps: (keymgr_dpe_scoreboard.sv:583) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'hbe6be8ffecdbd2432381ee3cedf9a0f1375eab732ec2c709b20cab3d9998a5050cffb4ea3ef67842f92e558772d42716e014ede531a24488682324693049ddce vs. act 'h0
        UVM_INFO @ 556455151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---