KMAC/MASKED Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.713m	19.936ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.490s	71.762us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.620s	274.954us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.660s	1.307ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.690s	6.296ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.240s	143.863us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.620s	274.954us	20	20	100.00
		kmac_csr_aliasing	9.690s	6.296ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.090s	17.804us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.680s	34.469us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.004h	752.364ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.442m	212.147ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.416m	93.784ms	5	5	100.00
		kmac_test_vectors_sha3_256	37.281m	87.809ms	5	5	100.00
		kmac_test_vectors_sha3_384	31.442m	144.522ms	5	5	100.00
		kmac_test_vectors_sha3_512	18.608m	258.223ms	5	5	100.00
		kmac_test_vectors_shake_128	3.758m	121.458ms	5	5	100.00
		kmac_test_vectors_shake_256	28.159m	242.648ms	5	5	100.00
		kmac_test_vectors_kmac	3.580s	209.795us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.840s	637.274us	5	5	100.00
V2	sideload	kmac_sideload	7.007m	19.311ms	50	50	100.00
V2	app	kmac_app	7.359m	92.148ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.705m	12.541ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.961m	54.662ms	50	50	100.00
V2	error	kmac_error	8.879m	21.303ms	50	50	100.00
V2	key_error	kmac_key_error	27.660s	22.516ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.620s	1.032ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.920s	11.456ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	18.440s	981.598us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.087m	6.154ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.600s	1.795ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.693m	183.903ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.230s	13.962us	50	50	100.00
V2	alert_test	kmac_alert_test	1.350s	411.326us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.110s	171.469us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.110s	171.469us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.490s	71.762us	5	5	100.00
		kmac_csr_rw	1.620s	274.954us	20	20	100.00
		kmac_csr_aliasing	9.690s	6.296ms	5	5	100.00
		kmac_same_csr_outstanding	3.180s	469.352us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.490s	71.762us	5	5	100.00
		kmac_csr_rw	1.620s	274.954us	20	20	100.00
		kmac_csr_aliasing	9.690s	6.296ms	5	5	100.00
		kmac_same_csr_outstanding	3.180s	469.352us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.760s	99.043us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.760s	99.043us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.760s	99.043us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.760s	99.043us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.180s	936.510us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.810m	8.626ms	5	5	100.00
		kmac_tl_intg_err	5.990s	250.758us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.990s	250.758us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.600s	1.795ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.713m	19.936ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.007m	19.311ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.760s	99.043us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.810m	8.626ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.810m	8.626ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.810m	8.626ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.713m	19.936ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.600s	1.795ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.810m	8.626ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.555m	51.355ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.713m	19.936ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.571m	22.644ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			939	940	99.89

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.55	99.27	94.45	99.89	80.99	97.15	99.38	97.71

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:525) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 5.kmac_stress_all_with_rand_reset.12039926742858424777727360667832217904061080177857546267830089667222456301289
      Line 376, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2781640448 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 2781640448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---