6181a2d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 42.000s | 172.738us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 11.000s | 18.303us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 10.000s | 22.322us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 12.000s | 68.550us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 9.000s | 36.886us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 11.000s | 61.745us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 10.000s | 22.322us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 9.000s | 36.886us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 52.000s | 2.444ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 27.000s | 1.063ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 42.000s | 135.523us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 1.417m | 226.837us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 28.600m | 5.508ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.367m | 1.162ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 21.000s | 113.415us | 60 | 60 | 100.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 9.000s | 48.484us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 20.000s | 51.810us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 10.000s | 58.318us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 9.000s | 69.387us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 14.000s | 81.650us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 14.000s | 81.650us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 11.000s | 18.303us | 5 | 5 | 100.00 |
| otbn_csr_rw | 10.000s | 22.322us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 9.000s | 36.886us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 15.908us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 11.000s | 18.303us | 5 | 5 | 100.00 |
| otbn_csr_rw | 10.000s | 22.322us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 9.000s | 36.886us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 15.908us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 246 | 246 | 100.00 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 44.305us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 105.715us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 13.000s | 66.026us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 12.000s | 323.056us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 57.685us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 10.000s | 16.728us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 84.973us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 16.850s | 1 | 2 | 50.00 | |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 8.000s | 23.413us | 9 | 10 | 90.00 |
| V2S | tl_intg_err | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| otbn_tl_intg_err | 54.000s | 293.805us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 41.000s | 258.879us | 17 | 20 | 85.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | prim_count_check | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 42.000s | 172.738us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 23.000s | 105.715us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 44.305us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 54.000s | 293.805us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 21.000s | 113.415us | 60 | 60 | 100.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 44.305us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 105.715us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 48.484us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 84.973us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 44.305us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 105.715us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 48.484us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 84.973us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 21.000s | 113.415us | 60 | 60 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 44.305us | 10 | 10 | 100.00 |
| otbn_dmem_err | 23.000s | 105.715us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 48.484us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 84.973us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 16.000s | 100.187us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 23.460us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 41.000s | 108.600us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 41.000s | 108.600us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 20.000s | 75.247us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 70.111us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 19.000s | 100.348us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 19.000s | 100.348us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 17.000s | 89.401us | 4 | 7 | 57.14 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 28.600m | 5.508ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 19.000s | 152.971us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.467m | 390.769us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 2.000m | 548.404us | 2 | 5 | 40.00 |
| V2S | TOTAL | 151 | 163 | 92.64 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 7.700m | 5.670ms | 3 | 10 | 30.00 |
| V3 | TOTAL | 3 | 10 | 30.00 | |||
| TOTAL | 566 | 585 | 96.75 |
Job returned non-zero exit code has 3 failures:
Test otbn_rf_base_intg_err has 1 failures.
0.otbn_rf_base_intg_err.71305167157425243256631711127218788729938568348838843600357205775704496267845
Log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 71305167157425243256631711127218788729938568348838843600357205775704496267845 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=2321277509 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_rf_base_intg_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_rf_base_intg_err.2321277509 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_rf_base_intg_err.2321277509 -covoverwrite' seed=71305167157425243256631711127218788729938568348838843600357205775704496267845 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_rf_base_intg_err_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 71305167157425243256631711127218788729938568348838843600357205775704496267845 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest
2025/09/06 06:54:45 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_mem_gnt_acc_err has 1 failures.
0.otbn_mem_gnt_acc_err.19346078246401408606088671560165336782958277151532525262811648129792048433103
Log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 19346078246401408606088671560165336782958277151532525262811648129792048433103 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3589343183 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_mem_gnt_acc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_mem_gnt_acc_err.3589343183 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_mem_gnt_acc_err.3589343183 -covoverwrite' seed=19346078246401408606088671560165336782958277151532525262811648129792048433103 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_mem_gnt_acc_err_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 19346078246401408606088671560165336782958277151532525262811648129792048433103 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest
2025/09/06 06:54:47 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn has 1 failures.
cov_merge
Log /nightly/current_run/scratch/master/otbn-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
UVM_ERROR (cip_base_vseq.sv:946) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
0.otbn_stress_all_with_rand_reset.64682197195371960758291681170174176251258333016554688487916025380925149229775
Line 184, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 969181270 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 969181270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_stress_all_with_rand_reset.56552274565266838234419599134295589083921657387567508367692839638000783234077
Line 218, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1904491449 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1904491449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
0.otbn_passthru_mem_tl_intg_err.87515357184007225045370435646897280036305803638335390858741849364013932644109
Line 88, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 174322438 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 174322438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_passthru_mem_tl_intg_err.64885234510898802072006775949794299361367396403251907623367290883016143986446
Line 98, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 26596564 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 26596564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:
1.otbn_sec_wipe_err.71621614891213906964183281428838080547652521340007658677453570669935244873319
Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 89401207 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 89401207 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 89401207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_sec_wipe_err.113156418265962148203418697656849652308833160133844652211112470974406627807283
Line 113, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38656048 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 38656048 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 38656048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 3 failures:
1.otbn_sec_cm.27844567277501962301630734430737697609847166018198903621920528995021465323302
Line 95, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 51070342 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 51070342 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 51070342 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 51070342 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 51070342 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
2.otbn_sec_cm.113772082004108989229559194043664723483675372820443486422386898823530544821294
Line 84, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 1115427 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 1115427 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 1115427 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 1115427 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1115427 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
2.otbn_stress_all_with_rand_reset.78419768781957801294569380065270155037061761005310364771168954958394071580251
Line 272, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 666639202 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 666639202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:718) virtual_sequencer [otbn_dmem_err_vseq] expect alert:fatal to fire has 1 failures:
4.otbn_stress_all_with_rand_reset.44962859263133849115297811472166605513201646292007476868165596696629516047932
Line 158, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21978049 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 21978049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
7.otbn_stress_all_with_rand_reset.74295021279741225434491487709683996629517684113620014678981703231684837824772
Line 351, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 706008520 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 706008520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
8.otbn_stress_all_with_rand_reset.27174389257192773484647208710328952960677770021634185710902024341181836457096
Line 222, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 907064020 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 907064020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
8.otbn_partial_wipe.95770536792575795037902878255426532300924388125149152712571973028263223935361
Line 105, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 11528464 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 11528464 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 11528464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: