ROM_CTRL/32KB Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.450s	190.099us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.420s	176.777us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.450s	554.726us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.110s	129.314us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.610s	520.181us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.900s	203.752us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.450s	554.726us	20	20	100.00
		rom_ctrl_csr_aliasing	5.610s	520.181us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.390s	1.170ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.350s	172.923us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.330s	2.130ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	27.250s	2.141ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.780s	233.045us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.480s	2.084ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.230s	202.701us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.230s	202.701us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.420s	176.777us	5	5	100.00
		rom_ctrl_csr_rw	7.450s	554.726us	20	20	100.00
		rom_ctrl_csr_aliasing	5.610s	520.181us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.760s	2.636ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.420s	176.777us	5	5	100.00
		rom_ctrl_csr_rw	7.450s	554.726us	20	20	100.00
		rom_ctrl_csr_aliasing	5.610s	520.181us	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.760s	2.636ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	31.150s	3.172ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.369m	1.370ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.042m	419.995us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.369m	1.370ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.369m	1.370ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.369m	1.370ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.369m	1.370ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.450s	190.099us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.450s	190.099us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.450s	190.099us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.042m	419.995us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
		rom_ctrl_kmac_err_chk	7.780s	233.045us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.550m	51.499ms	18	20	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	31.150s	3.172ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.369m	1.370ms	5	5	100.00
V2S		TOTAL			63	65	96.92
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.296m	3.308ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			264	266	99.25

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.54	99.73	98.81	100.00	100.00	100.00	98.98	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

    • 4.rom_ctrl_corrupt_sig_fatal_chk.88060594885238071753687221022725129834999443714182178474206950441429945297132
      Line 81, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 940710189 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 940710189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 17.rom_ctrl_corrupt_sig_fatal_chk.102806382288491691886047223932315177733586358337245327728678701924627066086162
      Line 102, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 3180332234 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 3180332234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---