RV_TIMER Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.860s	22.042us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.690s	67.804us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.660s	46.045us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.280s	172.386us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	26.776us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.100s	31.623us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.660s	46.045us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	26.776us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	10.590s	9.335ms	20	20	100.00
V2	disabled	rv_timer_disabled	2.980s	1.497ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.629m	1.031s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.629m	1.031s	10	10	100.00
V2	stress	rv_timer_stress_all	6.600s	9.599ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.750s	23.376us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.690s	12.226us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.230s	118.732us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.230s	118.732us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.690s	67.804us	5	5	100.00
		rv_timer_csr_rw	0.660s	46.045us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	26.776us	5	5	100.00
		rv_timer_same_csr_outstanding	0.910s	55.390us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.690s	67.804us	5	5	100.00
		rv_timer_csr_rw	0.660s	46.045us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	26.776us	5	5	100.00
		rv_timer_same_csr_outstanding	0.910s	55.390us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.190s	162.359us	5	5	100.00
		rv_timer_tl_intg_err	1.290s	128.945us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.290s	128.945us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	0.840s	20.756us	10	10	100.00
V3	max_value	rv_timer_max	0.790s	13.791us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	52.010s	24.181ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	100.00	100.00	78.66	--	100.00	100.00	100.00