SPI_DEVICE/1R1W Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.747m	199.290ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.670s	202.793us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.940s	95.572us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.530s	2.819ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.440s	3.984ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.380s	139.637us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.940s	95.572us	20	20	100.00
		spi_device_csr_aliasing	17.440s	3.984ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.010s	10.965us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.360s	71.244us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.160s	37.842us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.060s	2.091us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.080s	5.475us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	11.650s	1.198ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.650s	1.198ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.430s	15.745ms	50	50	100.00
		spi_device_tpm_sts_read	1.480s	137.848us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.940s	48.176ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	47.560s	68.647ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.950s	10.400ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.950s	10.400ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	17.850s	5.567ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	17.850s	5.567ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	17.850s	5.567ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	17.850s	5.567ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	17.850s	5.567ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	40.730s	74.427ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.443m	21.280ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.443m	21.280ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.443m	21.280ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.150s	3.730ms	50	50	100.00
		spi_device_read_buffer_direct	18.470s	2.208ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.443m	21.280ms	50	50	100.00
		spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.199m	306.230ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	35.920s	3.911ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	35.920s	3.911ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.747m	199.290ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.013m	282.556ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.106m	463.794ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.110s	12.695us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.100s	74.713us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.350s	300.324us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.350s	300.324us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.670s	202.793us	5	5	100.00
		spi_device_csr_rw	2.940s	95.572us	20	20	100.00
		spi_device_csr_aliasing	17.440s	3.984ms	5	5	100.00
		spi_device_same_csr_outstanding	4.820s	423.370us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.670s	202.793us	5	5	100.00
		spi_device_csr_rw	2.940s	95.572us	20	20	100.00
		spi_device_csr_aliasing	17.440s	3.984ms	5	5	100.00
		spi_device_same_csr_outstanding	4.820s	423.370us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.500s	429.995us	5	5	100.00
		spi_device_tl_intg_err	20.900s	1.033ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.900s	1.033ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.190m	83.990ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.81	99.11	96.56	71.19	89.36	98.40	95.76	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.72882630504498605845785477920137637942428701902915148610450409124881282547285
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3546649 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[95])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3546649 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3546649 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[991])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.54559605274298945121586452464322123950684856769907864490533515238029350266325
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4341629 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[33])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4341629 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4341629 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[929])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.43942078535227942417932868618761144589768966272711037658720535273009870735418
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2834124 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xac51cc [101011000101000111001100] vs 0x0 [0])
        UVM_ERROR @   2896124 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x28865e [1010001000011001011110] vs 0x0 [0])
        UVM_ERROR @   2925124 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf9a671 [111110011010011001110001] vs 0x0 [0])
        UVM_ERROR @   2979124 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdf3c18 [110111110011110000011000] vs 0x0 [0])
        UVM_ERROR @   3014124 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf9af06 [111110011010111100000110] vs 0x0 [0])