SRAM_CTRL/MAIN Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: `6181a2d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.607m	1.579ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.990s	125.895us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.010s	22.613us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.530s	1.136ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.070s	87.683us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.770s	1.119ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.010s	22.613us	20	20	100.00
		sram_ctrl_csr_aliasing	1.070s	87.683us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.760m	230.327ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.836m	5.796ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	18.647m	39.860ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.583m	28.954ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	35.792m	143.252ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.181m	20.726ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.719m	185.247ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.247m	210.580ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.821m	963.876us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.979m	52.553ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.638m	1.626ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.720m	3.293ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.935m	3.808ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.797m	18.898ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.770s	2.589ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.128h	606.219ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	139.874us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.250s	329.153us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.250s	329.153us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.990s	125.895us	5	5	100.00
		sram_ctrl_csr_rw	1.010s	22.613us	20	20	100.00
		sram_ctrl_csr_aliasing	1.070s	87.683us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	26.431us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.990s	125.895us	5	5	100.00
		sram_ctrl_csr_rw	1.010s	22.613us	20	20	100.00
		sram_ctrl_csr_aliasing	1.070s	87.683us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	26.431us	20	20	100.00
V2		TOTAL			789	790	99.87
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.490s	7.069ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.160s	15.572us	0	5	0.00
		sram_ctrl_tl_intg_err	3.700s	374.115us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.160s	15.572us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.700s	374.115us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.797m	18.898ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.797m	18.898ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.010s	22.613us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.247m	210.580ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.247m	210.580ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.247m	210.580ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.719m	185.247ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.490s	8.372ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.490s	7.069ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	9.730s	2.631ms	37	50	74.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.607m	1.579ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.607m	1.579ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.247m	210.580ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.160s	15.572us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.719m	185.247ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.160s	15.572us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.160s	15.572us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.607m	1.579ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.160s	15.572us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.849m	1.613ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1163	1190	97.73

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.11	92.90	85.46	100.00	98.02	98.61	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 13 failures:
- Test sram_ctrl_readback_err has 13 failures.
  - 4.sram_ctrl_readback_err.99733783333717420074794495267178901423380407436452593741540497379803225376354
    Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2923453293 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x36)
  UVM_INFO @ 2923453293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.sram_ctrl_readback_err.94142502233306624733894678719400183489618588514472442329853773106309234470570
    Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2434808728 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6f) != exp (0x64)
  UVM_INFO @ 2434808728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:
- Test sram_ctrl_sec_cm has 5 failures.
  - 0.sram_ctrl_sec_cm.557533041471366559260298583820469529664783781476129789003431464005189349944
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   1760722 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   1760722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_sec_cm.110760560112561508330641999422485247071910201909098027893421920925091873430370
    Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   7111134 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   7111134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Offending 'reqfifo_rvalid' has 5 failures:
- Test sram_ctrl_mubi_enc_err has 5 failures.
  - 8.sram_ctrl_mubi_enc_err.52357941692249731218271257959132892921844468541527024388264203998781476092619
    Line 106, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 6001424823 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 6001424823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.sram_ctrl_mubi_enc_err.40949945907795149456705285525646642081364678890880450072202065077859926376979
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2292216523 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2292216523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6801) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

18.sram_ctrl_mubi_enc_err.95370895386066261916982576782691902533867045286968905598696128538238443293658
Line 105, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/18.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 1308689632 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6801) { a_addr: 'h74141e74  a_data: 'h88  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h44  a_opcode: 'h1  a_user: 'h26152  d_param: 'h0  d_source: 'h44  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1308689632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4833) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

24.sram_ctrl_mubi_enc_err.104214377879754063647847859547468990809976305051064133652986235757202657549704
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/24.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 2988550287 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4833) { a_addr: 'habf0a23c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8d  a_opcode: 'h4  a_user: 'h244aa  d_param: 'h0  d_source: 'h8d  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2988550287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:849) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.sram_ctrl_stress_all_with_rand_reset.66126221752761189278497188083962148067711268938268906483557532618108170101327
    Line 106, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 409403860 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 409403860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 41.sram_ctrl_bijection.11810245483468297825064926297936045283906683128713845272647371052023852899930
    Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```