SRAM_CTRL/RET Simulation Results

Friday September 05 2025 17:04:13 UTC

GitHub Revision: 6181a2d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.759m	9.247ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.900s	68.986us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.030s	19.620us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.130s	122.325us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.930s	50.680us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.210s	316.465us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.030s	19.620us	20	20	100.00
		sram_ctrl_csr_aliasing	0.930s	50.680us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.280s	2.011ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.770s	187.426us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	20.919m	9.959ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.856m	7.442ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.286m	4.757ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.570m	33.016ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.830s	728.107us	50	50	100.00
V2	executable	sram_ctrl_executable	26.275m	10.973ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.563m	401.966us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.606m	50.482ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.653m	527.138us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.653m	484.130us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.745m	1.111ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.418m	88.024ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.160s	23.423us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.156h	33.782ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.010s	19.799us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.440s	480.787us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.440s	480.787us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.900s	68.986us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	19.620us	20	20	100.00
		sram_ctrl_csr_aliasing	0.930s	50.680us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.070s	94.076us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.900s	68.986us	5	5	100.00
		sram_ctrl_csr_rw	1.030s	19.620us	20	20	100.00
		sram_ctrl_csr_aliasing	0.930s	50.680us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.070s	94.076us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.800s	1.694ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.920s	10.612us	0	5	0.00
		sram_ctrl_tl_intg_err	3.300s	768.703us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.920s	10.612us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.300s	768.703us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.418m	88.024ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.418m	88.024ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.030s	19.620us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.275m	10.973ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.275m	10.973ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.275m	10.973ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.830s	728.107us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.430s	139.982us	47	50	94.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.800s	1.694ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.620s	45.488us	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.759m	9.247ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.759m	9.247ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.275m	10.973ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.920s	10.612us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.830s	728.107us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.920s	10.612us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.920s	10.612us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.759m	9.247ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.920s	10.612us	0	5	0.00
V2S		TOTAL			126	145	86.90
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.896m	1.651ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1169	1190	98.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.07	92.90	85.37	100.00	97.98	98.60	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:

  • Test sram_ctrl_readback_err has 11 failures.

    • 1.sram_ctrl_readback_err.59692067233979654942487579634990640533730682433665613338011851515607450947404
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  89857888 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x6f)
        UVM_INFO @  89857888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_readback_err.20334508588170487558572193153429807662836083785397157362472082042893329231308
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  36933935 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x35)
        UVM_INFO @  36933935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.13086518111854918795881357519392924486025651005832330457679008943073687827588
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8238447 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8238447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.114046116013928540671286906431392219879557283957083628721116101923232872046106
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5397176 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5397176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending 'reqfifo_rvalid' has 3 failures:

  • Test sram_ctrl_mubi_enc_err has 3 failures.

    • 12.sram_ctrl_mubi_enc_err.44420432924877647043298241627201652922947573163456686281442735503211638748848
      Line 106, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 109608363 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 109608363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 26.sram_ctrl_mubi_enc_err.47486239302459449716447059485087405307768069546176876856512993557602366940438
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  38623471 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  38623471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.66495161418681738017501640329152692622106369259109509744148988494793894958859
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1865632 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1865632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 5.sram_ctrl_csr_mem_rw_with_rand_reset.88650138658071476571999995986747322955694107089498032539794410500062636232972
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  27044228 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @  27044228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 22.sram_ctrl_stress_all_with_rand_reset.32561834555619202748664093023473261242099400542471051617811972161164641365026
      Line 179, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12150507313 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12150507313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---