AES/MASKED Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: `e14e4d4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	138.846us	1	1	100.00
V1	smoke	aes_smoke	5.000s	198.155us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	58.521us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	65.185us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	2.957ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	796.194us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	107.537us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	65.185us	20	20	100.00
		aes_csr_aliasing	5.000s	796.194us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	198.155us	50	50	100.00
		aes_config_error	9.000s	306.733us	50	50	100.00
		aes_stress	14.000s	520.668us	50	50	100.00
V2	key_length	aes_smoke	5.000s	198.155us	50	50	100.00
		aes_config_error	9.000s	306.733us	50	50	100.00
		aes_stress	14.000s	520.668us	50	50	100.00
V2	back2back	aes_stress	14.000s	520.668us	50	50	100.00
		aes_b2b	22.000s	558.494us	50	50	100.00
V2	backpressure	aes_stress	14.000s	520.668us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	198.155us	50	50	100.00
		aes_config_error	9.000s	306.733us	50	50	100.00
		aes_stress	14.000s	520.668us	50	50	100.00
		aes_alert_reset	11.000s	468.310us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	175.565us	50	50	100.00
		aes_config_error	9.000s	306.733us	50	50	100.00
		aes_alert_reset	11.000s	468.310us	50	50	100.00
V2	trigger_clear_test	aes_clear	35.000s	1.985ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	686.293us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	468.310us	50	50	100.00
V2	stress	aes_stress	14.000s	520.668us	50	50	100.00
V2	sideload	aes_stress	14.000s	520.668us	50	50	100.00
		aes_sideload	9.000s	376.046us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	179.178us	50	50	100.00
V2	stress_all	aes_stress_all	4.950m	11.994ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	57.862us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	231.980us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	231.980us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	58.521us	5	5	100.00
		aes_csr_rw	4.000s	65.185us	20	20	100.00
		aes_csr_aliasing	5.000s	796.194us	5	5	100.00
		aes_same_csr_outstanding	4.000s	138.796us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	58.521us	5	5	100.00
		aes_csr_rw	4.000s	65.185us	20	20	100.00
		aes_csr_aliasing	5.000s	796.194us	5	5	100.00
		aes_same_csr_outstanding	4.000s	138.796us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	627.880us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_cipher_fi	56.000s	10.006ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	180.587us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	180.587us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	180.587us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	180.587us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	511.819us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	5.523ms	5	5	100.00
		aes_tl_intg_err	5.000s	583.738us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	583.738us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	468.310us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	180.587us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	198.155us	50	50	100.00
		aes_stress	14.000s	520.668us	50	50	100.00
		aes_alert_reset	11.000s	468.310us	50	50	100.00
		aes_core_fi	56.000s	10.003ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	180.587us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	87.569us	50	50	100.00
		aes_stress	14.000s	520.668us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	520.668us	50	50	100.00
		aes_sideload	9.000s	376.046us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	87.569us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	87.569us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	87.569us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	87.569us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	87.569us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	520.668us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	520.668us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	796.032us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_cipher_fi	56.000s	10.006ms	335	350	95.71
		aes_ctr_fi	4.000s	57.066us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	796.032us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_cipher_fi	56.000s	10.006ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	56.000s	10.006ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	796.032us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_ctr_fi	4.000s	57.066us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_cipher_fi	56.000s	10.006ms	335	350	95.71
		aes_ctr_fi	4.000s	57.066us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	468.310us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_cipher_fi	56.000s	10.006ms	335	350	95.71
		aes_ctr_fi	4.000s	57.066us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_cipher_fi	56.000s	10.006ms	335	350	95.71
		aes_ctr_fi	4.000s	57.066us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_ctr_fi	4.000s	57.066us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	796.032us	50	50	100.00
		aes_control_fi	59.000s	10.026ms	279	300	93.00
		aes_cipher_fi	56.000s	10.006ms	335	350	95.71
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	35.000s	2.855ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 2.aes_cipher_fi.106003065573021332987618766323795659792226710174325914965472128661267722063413
    Line 150, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010124462 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010124462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_cipher_fi.27418561291522157144365285907458408074882020174732749944922216316930380937103
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012031241 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012031241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 3.aes_control_fi.27632298153713720533159834681492252756749492161104782474218996341687199771006
    Line 153, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026959983 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026959983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.aes_control_fi.37279739424581199231928130956119987503413226542263087319161212235793558384232
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10092967373 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10092967373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
Job timed out after * minutes has 10 failures:
- Test aes_control_fi has 8 failures.
  - 32.aes_control_fi.19592309569868405243647957605304682082578407896470413026234306407931073741269
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 42.aes_control_fi.67936100668112101303046532237283198813084884053391796408591704112181273934880
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.
- Test aes_cipher_fi has 2 failures.
  - 275.aes_cipher_fi.84965947650826006026503533735999951629931518396093979093366671332511212426725
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/275.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 297.aes_cipher_fi.2655965406795819025919601923919322864526707047871466926213859528202924371664
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/297.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.99358883654172090134471228567554812353570253815289763259982872983005860710217
Line 385, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2602663722 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.keymgr_sideload_agent.sequencer.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2602663722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.100099050626996239126654856122507279222972738267273436975964703932250615968405
Line 430, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 829678878 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 829678878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 3.aes_core_fi.7869790737639843114942562438505127928099996376448129821976685357848357690170
    Line 135, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10116675097 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10116675097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 48.aes_core_fi.89312453662863575815805379426748460163552265261901097710106097532451587072551
    Line 150, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002933899 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002933899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.59416851711492488285630885069697136140883132178469632069509894668251078658782
    Line 299, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 137249412 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 137249412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.46804621021840296751513658268310034612128831586785128626527793576500998568055
    Line 712, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 394993870 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 394993870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.21554545057458789811632828936540401142948223668661292727548230314477496037247
    Line 152, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 228515714 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 228515714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.log