AES/UNMASKED Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: `e14e4d4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	54.970us	1	1	100.00
V1	smoke	aes_smoke	5.000s	226.620us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	86.759us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	57.651us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	215.070us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	471.599us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	135.430us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	57.651us	20	20	100.00
		aes_csr_aliasing	5.000s	471.599us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	226.620us	50	50	100.00
		aes_config_error	6.000s	546.251us	50	50	100.00
		aes_stress	5.000s	189.172us	50	50	100.00
V2	key_length	aes_smoke	5.000s	226.620us	50	50	100.00
		aes_config_error	6.000s	546.251us	50	50	100.00
		aes_stress	5.000s	189.172us	50	50	100.00
V2	back2back	aes_stress	5.000s	189.172us	50	50	100.00
		aes_b2b	9.000s	1.580ms	50	50	100.00
V2	backpressure	aes_stress	5.000s	189.172us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	226.620us	50	50	100.00
		aes_config_error	6.000s	546.251us	50	50	100.00
		aes_stress	5.000s	189.172us	50	50	100.00
		aes_alert_reset	4.000s	87.869us	49	50	98.00
V2	failure_test	aes_man_cfg_err	5.000s	160.235us	50	50	100.00
		aes_config_error	6.000s	546.251us	50	50	100.00
		aes_alert_reset	4.000s	87.869us	49	50	98.00
V2	trigger_clear_test	aes_clear	6.000s	507.598us	48	50	96.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	296.050us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	87.869us	49	50	98.00
V2	stress	aes_stress	5.000s	189.172us	50	50	100.00
V2	sideload	aes_stress	5.000s	189.172us	50	50	100.00
		aes_sideload	4.000s	60.989us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	118.502us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	3.313ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	181.861us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	209.385us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	209.385us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	86.759us	5	5	100.00
		aes_csr_rw	5.000s	57.651us	20	20	100.00
		aes_csr_aliasing	5.000s	471.599us	5	5	100.00
		aes_same_csr_outstanding	4.000s	116.980us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	86.759us	5	5	100.00
		aes_csr_rw	5.000s	57.651us	20	20	100.00
		aes_csr_aliasing	5.000s	471.599us	5	5	100.00
		aes_same_csr_outstanding	4.000s	116.980us	20	20	100.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	10.000s	772.958us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_cipher_fi	42.000s	10.022ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	116.372us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	116.372us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	116.372us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	116.372us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	99.610us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	875.269us	5	5	100.00
		aes_tl_intg_err	9.000s	836.066us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	836.066us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	87.869us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	116.372us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	226.620us	50	50	100.00
		aes_stress	5.000s	189.172us	50	50	100.00
		aes_alert_reset	4.000s	87.869us	49	50	98.00
		aes_core_fi	4.350m	10.009ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	116.372us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	80.580us	50	50	100.00
		aes_stress	5.000s	189.172us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	189.172us	50	50	100.00
		aes_sideload	4.000s	60.989us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	80.580us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	80.580us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	80.580us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	80.580us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	80.580us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	189.172us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	189.172us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	217.688us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_cipher_fi	42.000s	10.022ms	328	350	93.71
		aes_ctr_fi	4.000s	243.037us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	217.688us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_cipher_fi	42.000s	10.022ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	42.000s	10.022ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	217.688us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_ctr_fi	4.000s	243.037us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_cipher_fi	42.000s	10.022ms	328	350	93.71
		aes_ctr_fi	4.000s	243.037us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	87.869us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_cipher_fi	42.000s	10.022ms	328	350	93.71
		aes_ctr_fi	4.000s	243.037us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_cipher_fi	42.000s	10.022ms	328	350	93.71
		aes_ctr_fi	4.000s	243.037us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_ctr_fi	4.000s	243.037us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	217.688us	50	50	100.00
		aes_control_fi	48.000s	200.000ms	278	300	92.67
		aes_cipher_fi	42.000s	10.022ms	328	350	93.71
V2S		TOTAL			935	985	94.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	18.000s	775.475us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Failure Buckets

Job timed out after * minutes has 26 failures:
- Test aes_control_fi has 15 failures.
  - 22.aes_control_fi.65767548742378810007690846733884086496268067898325513466131414163432771512922
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 103.aes_control_fi.97503838659982324765346839988870415601996662011105078174028769565962653960554
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/103.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 10 failures.
  - 24.aes_cipher_fi.82008056933926772833279214116896282988821185260365591459299924448950868753444
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 57.aes_cipher_fi.60916279811848637957958529078137487518328639418135316767979634483615561688932
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_ctr_fi has 1 failures.
  - 31.aes_ctr_fi.95062437788336277871369790172195302384053039115874497568845643242911672145439
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 31.aes_cipher_fi.1557627600969223954878657460478975256140257659756774518610201044978630327273
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004376603 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004376603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.aes_cipher_fi.77140072195785991596768011722367771072669355786562530657406498834378452373612
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016039182 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016039182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.22657318660509662368668546474271239209273590844680444307738460706931686701101
Line 1226, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 775474698 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 775474698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.55357400135588755503839059705134552155575455518231753309393337346923098228728
Line 883, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 968538282 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.keymgr_sideload_agent.sequencer.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 968538282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 37.aes_control_fi.100612778921932881779684354955214742518861638262731476891528002090369008806716
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/37.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003242731 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003242731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 150.aes_control_fi.64855799336325285969191533471930659961392098381298614281239604200903867791619
    Line 147, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/150.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012124713 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012124713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 2 failures:
- Test aes_clear has 2 failures.
  - 2.aes_clear.57148050159258040407096024822501964694403434938321559237352644588311310884146
    Line 4555, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_clear/latest/run.log
```
  UVM_FATAL @ 136709608 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 2
           TEST FAILED MESSAGES DID NOT MATCH

                 0 ef 	 8e 	 fa 	 0
                 1 02 	 85 	 2f 	 0
```
  - 20.aes_clear.10596244897513763389913594001679296154354429530331285646198235857738918183632
    Line 3767, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_clear/latest/run.log
```
  UVM_FATAL @  42271876 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 4e 	 ed 	 f6 	 0
                 1 d9 	 d9 	 4b 	 0
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 31.aes_core_fi.49273552368333617012658716000917700409265090297697744693308971228854332899968
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015148561 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015148561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 67.aes_core_fi.30357415596448576812283861739225752943551596501232607897988969128119401790879
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003487805 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003487805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 0.aes_core_fi.49753925082480333871961562709987789673522686342518276294681426212816057845666
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019545347 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x929c2f84, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10019545347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

46.aes_alert_reset.3975978817406083620316992938090906063545234313880491448998838029540995063668
Line 2346, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/46.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 25392594 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 25352594 PS)
  UVM_ERROR @  25392594 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  25392594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 48.aes_core_fi.8322359992655392973550150019441580432581215395584053739680162704895729554395
    Line 131, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009470923 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x16a69084, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10009470923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 54.aes_core_fi.698720650145686488118472043209991674890345630931263008173718064604589070856
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051669980 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051669980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 274.aes_control_fi.23958277299221668314558667029342505801229798317264131384561423647004195462608
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/274.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test aes has 1 failures.

cov_merge
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_merge/merged/cov_merge.log

  [Executing]:
  make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'

  [make]: cov_merge
  imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
  *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
  Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
  Created log file /nightly/current_run/opentitan/startup.log
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aes has 1 failures.
  - cov_report
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/cov_report/cov_report.log