CSRNG Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	93.486us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	21.744us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	72.633us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	56.000s	5.156ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	289.971us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	124.162us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	72.633us	20	20	100.00
		csrng_csr_aliasing	7.000s	289.971us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	23.000s	1.560ms	185	200	92.50
V2	alerts	csrng_alert	53.000s	3.916ms	500	500	100.00
V2	err	csrng_err	8.000s	1.727us	470	500	94.00
V2	cmds	csrng_cmds	7.300m	37.057ms	50	50	100.00
V2	life cycle	csrng_cmds	7.300m	37.057ms	50	50	100.00
V2	stress_all	csrng_stress_all	40.817m	186.752ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	15.666us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	175.581us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	619.318us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	619.318us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	21.744us	5	5	100.00
		csrng_csr_rw	5.000s	72.633us	20	20	100.00
		csrng_csr_aliasing	7.000s	289.971us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	519.238us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	21.744us	5	5	100.00
		csrng_csr_rw	5.000s	72.633us	20	20	100.00
		csrng_csr_aliasing	7.000s	289.971us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	519.238us	20	20	100.00
V2		TOTAL			1392	1440	96.67
V2S	tl_intg_err	csrng_sec_cm	7.000s	100.171us	5	5	100.00
		csrng_tl_intg_err	10.000s	586.360us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	166.928us	50	50	100.00
		csrng_csr_rw	5.000s	72.633us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	53.000s	3.916ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	40.817m	186.752ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	53.000s	3.916ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	40.817m	186.752ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	53.000s	3.916ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	10.000s	586.360us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
		csrng_sec_cm	7.000s	100.171us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	23.000s	1.560ms	185	200	92.50
		csrng_err	8.000s	1.727us	470	500	94.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	6.500m	17.006ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1582	1630	97.06

Failure Buckets

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 16 failures:

  • Test csrng_err has 16 failures.

    • 27.csrng_err.32029764116277111504667357952674090090775589100422181900162202587517353229619
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/27.csrng_err/latest/run.log

        UVM_FATAL @   3234431 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   3234431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 41.csrng_err.87476264645716853940152403516473722985319327826524908036330098058882539973621
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/41.csrng_err/latest/run.log

        UVM_FATAL @   6406177 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   6406177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 14 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_err_vseq] has 14 failures:

  • Test csrng_err has 14 failures.

    • 9.csrng_err.108466611308887436545736476641008776252389375171419914678969341800616204721587
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/9.csrng_err/latest/run.log

        UVM_FATAL @   3464800 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   3464800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 21.csrng_err.50535292485493401635463276950097363055471720360197457673056692908355533236399
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/21.csrng_err/latest/run.log

        UVM_FATAL @   1726868 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   1726868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 12 more failures.

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_intr_vseq] has 8 failures:

  • Test csrng_intr has 8 failures.

    • 0.csrng_intr.45709507077625632923676710476217231876676664260307790279346726326166609357101
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

        UVM_FATAL @ 134402115 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 134402115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 26.csrng_intr.33383208441328931779985168218314632740414169973817112694209762897201615266789
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/26.csrng_intr/latest/run.log

        UVM_FATAL @ 101315109 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 101315109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 7 failures:

  • Test csrng_intr has 7 failures.

    • 17.csrng_intr.6080504532281033170800403291492245704413862077054534231765324435811699342217
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/17.csrng_intr/latest/run.log

        UVM_FATAL @ 127801446 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 127801446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 31.csrng_intr.19032132737722359523373772244665781062361341048674824339739021682593842193766
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/31.csrng_intr/latest/run.log

        UVM_FATAL @ 132601111 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 132601111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

  • Test csrng_stress_all has 3 failures.

    • 19.csrng_stress_all.8484118312686554107059703858066220048011783022207236001536140671333403640541
      Line 142, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log

        UVM_ERROR @ 6610153333 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 6610153333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 24.csrng_stress_all.36346114936677851936095074343774909259501973500855414970970555873730235585088
      Line 138, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/24.csrng_stress_all/latest/run.log

        UVM_ERROR @  54872207 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  54872207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Job returned non-zero exit code has 1 failures:

  • Test csrng has 1 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_merge/merged/cov_merge.log

        [Executing]:
        make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
      
        [make]: cov_merge
        imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
        *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
        Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
        Created log file /nightly/current_run/opentitan/startup.log
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test csrng has 1 failures.
    • cov_report
      Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.log