e14e4d4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | dma_memory_smoke | dma_memory_smoke | 9.000s | 691.609us | 25 | 25 | 100.00 |
| V1 | dma_handshake_smoke | dma_handshake_smoke | 14.000s | 1.217ms | 25 | 25 | 100.00 |
| V1 | dma_generic_smoke | dma_generic_smoke | 10.000s | 2.437ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | dma_csr_hw_reset | 3.000s | 35.225us | 5 | 5 | 100.00 |
| V1 | csr_rw | dma_csr_rw | 3.000s | 57.148us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | dma_csr_bit_bash | 16.000s | 1.480ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | dma_csr_aliasing | 10.000s | 1.796ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | dma_csr_mem_rw_with_rand_reset | 4.000s | 31.103us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | dma_csr_rw | 3.000s | 57.148us | 20 | 20 | 100.00 |
| dma_csr_aliasing | 10.000s | 1.796ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | dma_memory_region_lock | dma_memory_region_lock | 1.100m | 14.579ms | 5 | 5 | 100.00 |
| V2 | dma_memory_tl_error | dma_memory_stress | 5.283m | 125.271ms | 3 | 3 | 100.00 |
| V2 | dma_handshake_tl_error | dma_handshake_stress | 9.333m | 85.064ms | 3 | 3 | 100.00 |
| V2 | dma_handshake_stress | dma_handshake_stress | 9.333m | 85.064ms | 3 | 3 | 100.00 |
| V2 | dma_memory_stress | dma_memory_stress | 5.283m | 125.271ms | 3 | 3 | 100.00 |
| V2 | dma_generic_stress | dma_generic_stress | 13.083m | 281.949ms | 5 | 5 | 100.00 |
| V2 | dma_handshake_mem_buffer_overflow | dma_handshake_stress | 9.333m | 85.064ms | 3 | 3 | 100.00 |
| V2 | dma_abort | dma_abort | 16.000s | 1.491ms | 5 | 5 | 100.00 |
| V2 | dma_stress_all | dma_stress_all | 2.967m | 46.174ms | 3 | 3 | 100.00 |
| V2 | alert_test | dma_alert_test | 3.000s | 44.175us | 50 | 50 | 100.00 |
| V2 | intr_test | dma_intr_test | 3.000s | 48.157us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | dma_tl_errors | 5.000s | 606.134us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | dma_tl_errors | 5.000s | 606.134us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | dma_csr_hw_reset | 3.000s | 35.225us | 5 | 5 | 100.00 |
| dma_csr_rw | 3.000s | 57.148us | 20 | 20 | 100.00 | ||
| dma_csr_aliasing | 10.000s | 1.796ms | 5 | 5 | 100.00 | ||
| dma_same_csr_outstanding | 4.000s | 138.549us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | dma_csr_hw_reset | 3.000s | 35.225us | 5 | 5 | 100.00 |
| dma_csr_rw | 3.000s | 57.148us | 20 | 20 | 100.00 | ||
| dma_csr_aliasing | 10.000s | 1.796ms | 5 | 5 | 100.00 | ||
| dma_same_csr_outstanding | 4.000s | 138.549us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 164 | 164 | 100.00 | |||
| V2S | dma_illegal_addr_range | dma_mem_enabled | 20.000s | 391.398us | 5 | 5 | 100.00 |
| dma_generic_stress | 13.083m | 281.949ms | 5 | 5 | 100.00 | ||
| dma_handshake_stress | 9.333m | 85.064ms | 3 | 3 | 100.00 | ||
| V2S | dma_config_lock | dma_config_lock | 14.000s | 720.144us | 15 | 15 | 100.00 |
| V2S | tl_intg_err | dma_tl_intg_err | 5.000s | 377.879us | 20 | 20 | 100.00 |
| dma_sec_cm | 3.000s | 17.024us | 5 | 5 | 100.00 | ||
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| Unmapped tests | dma_short_transfer | 3.400m | 29.599ms | 25 | 25 | 100.00 | |
| dma_longer_transfer | 1.167m | 13.894ms | 5 | 5 | 100.00 | ||
| dma_stress_all_with_rand_reset | 20.000s | 4.320ms | 0 | 1 | 0.00 | ||
| TOTAL | 394 | 395 | 99.75 |
UVM_ERROR @ *ps: (cip_base_vseq.sv:946) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.dma_stress_all_with_rand_reset.50162411873968826076577947614288843973541822431979060485435871472480152418159
Line 115, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4320161140ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4320161140ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code has 1 failures:
cov_merge
Log /nightly/current_run/scratch/master/dma-sim-xcelium/cov_merge/merged/cov_merge.log
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
[make]: cov_merge
imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
*I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
Created log file /nightly/current_run/opentitan/startup.log
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: