EDN Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.290s	20.547us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.920s	15.809us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.020s	15.258us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.590s	260.554us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.540s	480.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.560s	32.587us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.020s	15.258us	20	20	100.00
		edn_csr_aliasing	1.540s	480.939us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.643m	10.985ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.643m	10.985ms	300	300	100.00
V2	genbits	edn_genbits	1.643m	10.985ms	300	300	100.00
V2	interrupts	edn_intr	1.500s	20.971us	50	50	100.00
V2	alerts	edn_alert	1.600s	26.378us	200	200	100.00
V2	errs	edn_err	1.420s	22.632us	100	100	100.00
V2	disable	edn_disable	1.240s	15.708us	50	50	100.00
		edn_disable_auto_req_mode	1.830s	103.865us	50	50	100.00
V2	stress_all	edn_stress_all	5.300s	369.952us	50	50	100.00
V2	intr_test	edn_intr_test	0.910s	27.765us	50	50	100.00
V2	alert_test	edn_alert_test	1.400s	31.933us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.680s	134.194us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.680s	134.194us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.920s	15.809us	5	5	100.00
		edn_csr_rw	1.020s	15.258us	20	20	100.00
		edn_csr_aliasing	1.540s	480.939us	5	5	100.00
		edn_same_csr_outstanding	1.320s	53.512us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.920s	15.809us	5	5	100.00
		edn_csr_rw	1.020s	15.258us	20	20	100.00
		edn_csr_aliasing	1.540s	480.939us	5	5	100.00
		edn_same_csr_outstanding	1.320s	53.512us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	8.140s	1.410ms	5	5	100.00
		edn_tl_intg_err	3.010s	184.510us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.320s	29.679us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.600s	26.378us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.140s	1.410ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.140s	1.410ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.140s	1.410ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.140s	1.410ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.600s	26.378us	200	200	100.00
		edn_sec_cm	8.140s	1.410ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.600s	26.378us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.010s	184.510us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.670m	20.049ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1117	1130	98.85

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.57	98.87	94.23	97.02	91.86	96.33	97.56	93.13

Failure Buckets

• Job timed out after * minutes has 12 failures:
  • Test edn_stress_all_with_rand_reset has 12 failures.

    • 9.edn_stress_all_with_rand_reset.44177606644851752619487501579487765469201039708542919320642601462181426338199
      Log /nightly/current_run/scratch/master/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 11.edn_stress_all_with_rand_reset.101967950110745723842371269868549026407050900342786247164906609468562000592701
      Log /nightly/current_run/scratch/master/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 10 more failures.

• UVM_ERROR (cip_base_vseq.sv:849) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 36.edn_stress_all_with_rand_reset.83006614079711375198137304209570670972945562014467305709330451708373408920675
      Line 263, in log /nightly/current_run/scratch/master/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2482603778 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2482603778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---