HMAC Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	12.310s	646.530us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.190s	77.238us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.030s	30.256us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.590s	2.197ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.110s	572.879us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.967m	77.055ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.030s	30.256us	20	20	100.00
		hmac_csr_aliasing	6.110s	572.879us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.193m	26.148ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.691m	1.534ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.799m	43.138ms	30	30	100.00
		hmac_test_sha384_vectors	8.940m	57.574ms	75	75	100.00
		hmac_test_sha512_vectors	9.062m	53.398ms	75	75	100.00
		hmac_test_hmac256_vectors	14.120s	1.219ms	50	50	100.00
		hmac_test_hmac384_vectors	16.470s	789.839us	60	60	100.00
		hmac_test_hmac512_vectors	19.820s	417.887us	75	75	100.00
V2	burst_wr	hmac_burst_wr	49.160s	17.753ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	18.220m	27.658ms	10	10	100.00
V2	error	hmac_error	1.576m	11.197ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.128m	70.878ms	10	10	100.00
V2	save_and_restore	hmac_smoke	12.310s	646.530us	10	10	100.00
		hmac_long_msg	1.193m	26.148ms	10	10	100.00
		hmac_back_pressure	1.691m	1.534ms	25	25	100.00
		hmac_datapath_stress	18.220m	27.658ms	10	10	100.00
		hmac_burst_wr	49.160s	17.753ms	50	50	100.00
		hmac_stress_all	1.029h	127.061ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	12.310s	646.530us	10	10	100.00
		hmac_long_msg	1.193m	26.148ms	10	10	100.00
		hmac_back_pressure	1.691m	1.534ms	25	25	100.00
		hmac_datapath_stress	18.220m	27.658ms	10	10	100.00
		hmac_wipe_secret	2.128m	70.878ms	10	10	100.00
		hmac_test_sha256_vectors	3.799m	43.138ms	30	30	100.00
		hmac_test_sha384_vectors	8.940m	57.574ms	75	75	100.00
		hmac_test_sha512_vectors	9.062m	53.398ms	75	75	100.00
		hmac_test_hmac256_vectors	14.120s	1.219ms	50	50	100.00
		hmac_test_hmac384_vectors	16.470s	789.839us	60	60	100.00
		hmac_test_hmac512_vectors	19.820s	417.887us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	12.310s	646.530us	10	10	100.00
		hmac_long_msg	1.193m	26.148ms	10	10	100.00
		hmac_back_pressure	1.691m	1.534ms	25	25	100.00
		hmac_datapath_stress	18.220m	27.658ms	10	10	100.00
		hmac_burst_wr	49.160s	17.753ms	50	50	100.00
		hmac_error	1.576m	11.197ms	10	10	100.00
		hmac_wipe_secret	2.128m	70.878ms	10	10	100.00
		hmac_test_sha256_vectors	3.799m	43.138ms	30	30	100.00
		hmac_test_sha384_vectors	8.940m	57.574ms	75	75	100.00
		hmac_test_sha512_vectors	9.062m	53.398ms	75	75	100.00
		hmac_test_hmac256_vectors	14.120s	1.219ms	50	50	100.00
		hmac_test_hmac384_vectors	16.470s	789.839us	60	60	100.00
		hmac_test_hmac512_vectors	19.820s	417.887us	75	75	100.00
		hmac_stress_all	1.029h	127.061ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.029h	127.061ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.890s	84.081us	50	50	100.00
V2	intr_test	hmac_intr_test	0.860s	11.591us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.200s	232.866us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.200s	232.866us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.190s	77.238us	5	5	100.00
		hmac_csr_rw	1.030s	30.256us	20	20	100.00
		hmac_csr_aliasing	6.110s	572.879us	5	5	100.00
		hmac_same_csr_outstanding	2.200s	498.143us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.190s	77.238us	5	5	100.00
		hmac_csr_rw	1.030s	30.256us	20	20	100.00
		hmac_csr_aliasing	6.110s	572.879us	5	5	100.00
		hmac_same_csr_outstanding	2.200s	498.143us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.350s	423.254us	5	5	100.00
		hmac_tl_intg_err	3.880s	286.807us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.880s	286.807us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	12.310s	646.530us	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.990s	584.039us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.477m	71.463ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.220s	243.810us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.53	99.79	96.85	100.00	100.00	99.67	97.14	47.30