KEYMGR Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	25.890s	17.240ms	50	50	100.00
V1	random	keymgr_random	1.093m	8.993ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.210s	25.238us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.570s	121.320us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.660s	874.201us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.210s	1.485ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.850s	53.818us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.570s	121.320us	20	20	100.00
		keymgr_csr_aliasing	10.210s	1.485ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.016m	6.382ms	50	50	100.00
V2	sideload	keymgr_sideload	18.210s	894.488us	49	50	98.00
		keymgr_sideload_kmac	42.530s	6.208ms	50	50	100.00
		keymgr_sideload_aes	42.440s	15.345ms	50	50	100.00
		keymgr_sideload_otbn	46.850s	10.548ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.450s	1.316ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	5.950s	132.686us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	18.500s	785.222us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	58.500s	17.358ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	14.540s	678.553us	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	16.990s	2.648ms	50	50	100.00
V2	stress_all	keymgr_stress_all	6.000m	17.681ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.070s	12.813us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.380s	27.722us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.960s	108.465us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.960s	108.465us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.210s	25.238us	5	5	100.00
		keymgr_csr_rw	1.570s	121.320us	20	20	100.00
		keymgr_csr_aliasing	10.210s	1.485ms	5	5	100.00
		keymgr_same_csr_outstanding	3.320s	149.423us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.210s	25.238us	5	5	100.00
		keymgr_csr_rw	1.570s	121.320us	20	20	100.00
		keymgr_csr_aliasing	10.210s	1.485ms	5	5	100.00
		keymgr_same_csr_outstanding	3.320s	149.423us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
		keymgr_tl_intg_err	8.570s	1.083ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.900s	109.378us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.900s	109.378us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.900s	109.378us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.900s	109.378us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.440s	3.082ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.570s	1.083ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.900s	109.378us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.016m	6.382ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.093m	8.993ms	50	50	100.00
		keymgr_csr_rw	1.570s	121.320us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.093m	8.993ms	50	50	100.00
		keymgr_csr_rw	1.570s	121.320us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.093m	8.993ms	50	50	100.00
		keymgr_csr_rw	1.570s	121.320us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.950s	132.686us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	14.540s	678.553us	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	14.540s	678.553us	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.093m	8.993ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	22.890s	3.485ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	15.430s	6.750ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.950s	132.686us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	15.430s	6.750ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	15.430s	6.750ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	15.430s	6.750ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.850s	1.436ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	15.430s	6.750ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	19.130s	694.689us	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1089	1110	98.11

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	99.13	97.99	98.44	100.00	99.01	97.71	91.13

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test keymgr_stress_all_with_rand_reset has 16 failures.
  - 1.keymgr_stress_all_with_rand_reset.35147131899991219074019889068663938276226912719753353314269343204689971859798
    Line 665, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 193947733 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 193947733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.keymgr_stress_all_with_rand_reset.32577577018907095874454268704727835092288751042928237086840492522114338025067
    Line 623, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 242009766 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 242009766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_sideload has 1 failures.
  - 4.keymgr_sideload.21636003231482076990565804489943375589087530958761423894115288615383096901122
    Line 101, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_sideload/latest/run.log
```
  UVM_ERROR @   7206833 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   7206833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sw_invalid_input has 1 failures.
  - 6.keymgr_sw_invalid_input.64965939321102530452521119067599287399009137395130200119813383355992596919241
    Line 282, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @ 115639195 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 115639195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_kmac_rsp_err has 1 failures.
  - 27.keymgr_kmac_rsp_err.24704822660632891789333513961689312606584009014350428618208586952807897067279
    Line 411, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @ 785221863 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 785221863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

1.keymgr_stress_all.71629652030379099479692422312102798499300592119273033044076297667071832237922
Line 1705, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 255876536 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4203643557266282049595936017044792375774985431379880450823915966042017952800758879003713993005376414734916336328676881228363527459862989036780394054999523 [0x5042fb50ab23611dcff1e8d9573dbc6bc02e485d10ed45630c32ff6daea792f0737126077de88771d383f66084f6a6cc22c8c8142ff3224fab786b76216cdde3] vs 4203643557266282049595936017044792375774985431379880450823915966042017952800758879003713993005376414734916336328676881228363527459862989036780394054999523 [0x5042fb50ab23611dcff1e8d9573dbc6bc02e485d10ed45630c32ff6daea792f0737126077de88771d383f66084f6a6cc22c8c8142ff3224fab786b76216cdde3]) AES key at state StOwnerKey for Sealing Aes
  UVM_INFO @ 255876536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

38.keymgr_lc_disable.36666533493332295998900078380555140513578310883498077003470942145262797337072
Line 581, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 330332648 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (1876475542757211641607278445814733980490237098043926350421897674985927139854277455753296143614913299493164036519861620748175519376965191052350829851642925 [0x23d4057a07524dbadc4279a3e553902231a13b9e367c2400970939f8d5585a26e1a59cc0ca8601046010e8f1768504831651465cd783f78a15b4d7d00dbd0c2d] vs 1876475542757211641607278445814733980490237098043926350421897674985927139854277455753296143614913299493164036519861620748175519376965191052350829851642925 [0x23d4057a07524dbadc4279a3e553902231a13b9e367c2400970939f8d5585a26e1a59cc0ca8601046010e8f1768504831651465cd783f78a15b4d7d00dbd0c2d]) KMAC key at state StOwnerIntKey for Attestation Kmac
  UVM_INFO @ 330332648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---