| V1 |
smoke |
keymgr_dpe_smoke |
5.797m |
17.846ms |
50 |
50 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.740s |
28.881us |
5 |
5 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.320s |
261.687us |
20 |
20 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
8.470s |
3.828ms |
5 |
5 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
5.150s |
949.789us |
5 |
5 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.940s |
61.548us |
20 |
20 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.320s |
261.687us |
20 |
20 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.150s |
949.789us |
5 |
5 |
100.00 |
| V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.070s |
12.606us |
50 |
50 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.550s |
206.545us |
50 |
50 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
4.020s |
132.318us |
20 |
20 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
4.020s |
132.318us |
20 |
20 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.740s |
28.881us |
5 |
5 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.320s |
261.687us |
20 |
20 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.150s |
949.789us |
5 |
5 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.800s |
189.424us |
20 |
20 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.740s |
28.881us |
5 |
5 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.320s |
261.687us |
20 |
20 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.150s |
949.789us |
5 |
5 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.800s |
189.424us |
20 |
20 |
100.00 |
| V2 |
|
TOTAL |
|
|
140 |
140 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
16.980s |
925.108us |
5 |
5 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
4.000s |
232.887us |
20 |
20 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
3.590s |
179.977us |
20 |
20 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
3.590s |
179.977us |
20 |
20 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
3.590s |
179.977us |
20 |
20 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
3.590s |
179.977us |
20 |
20 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
5.700s |
795.549us |
20 |
20 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
16.980s |
925.108us |
5 |
5 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
16.980s |
925.108us |
5 |
5 |
100.00 |
| V2S |
|
TOTAL |
|
|
65 |
65 |
100.00 |
|
|
TOTAL |
|
|
310 |
310 |
100.00 |