KMAC/MASKED Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.460m	8.860ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.550s	116.954us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.520s	35.893us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.700s	2.006ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.730s	794.083us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.410s	323.840us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.520s	35.893us	20	20	100.00
		kmac_csr_aliasing	9.730s	794.083us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.070s	41.469us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.950s	137.462us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	50.949m	171.907ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.487m	38.146ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.634m	71.969ms	5	5	100.00
		kmac_test_vectors_sha3_256	31.460m	60.228ms	5	5	100.00
		kmac_test_vectors_sha3_384	20.389m	59.313ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.597m	190.481ms	5	5	100.00
		kmac_test_vectors_shake_128	44.084m	110.412ms	5	5	100.00
		kmac_test_vectors_shake_256	37.524m	181.135ms	5	5	100.00
		kmac_test_vectors_kmac	3.270s	328.905us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.790s	189.425us	5	5	100.00
V2	sideload	kmac_sideload	8.484m	53.079ms	50	50	100.00
V2	app	kmac_app	6.819m	16.010ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.236m	8.849ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.487m	38.213ms	49	50	98.00
V2	error	kmac_error	8.222m	88.065ms	50	50	100.00
V2	key_error	kmac_key_error	17.670s	7.923ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.640s	472.023us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.600s	28.696ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.840s	12.734ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.561m	48.573ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	40.140s	920.843us	50	50	100.00
V2	stress_all	kmac_stress_all	58.602m	293.802ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.180s	58.104us	50	50	100.00
V2	alert_test	kmac_alert_test	1.400s	582.562us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.240s	164.466us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.240s	164.466us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.550s	116.954us	5	5	100.00
		kmac_csr_rw	1.520s	35.893us	20	20	100.00
		kmac_csr_aliasing	9.730s	794.083us	5	5	100.00
		kmac_same_csr_outstanding	3.180s	227.158us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.550s	116.954us	5	5	100.00
		kmac_csr_rw	1.520s	35.893us	20	20	100.00
		kmac_csr_aliasing	9.730s	794.083us	5	5	100.00
		kmac_same_csr_outstanding	3.180s	227.158us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.230s	1.339ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.230s	1.339ms	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.230s	1.339ms	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.230s	1.339ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.460s	384.261us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.565m	9.183ms	5	5	100.00
		kmac_tl_intg_err	5.900s	534.442us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.900s	534.442us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	40.140s	920.843us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.460m	8.860ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.484m	53.079ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.230s	1.339ms	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.565m	9.183ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.565m	9.183ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.565m	9.183ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.460m	8.860ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	40.140s	920.843us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.565m	9.183ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.141m	14.844ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.460m	8.860ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.543m	4.681ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			935	940	99.47

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.35	99.27	94.45	99.89	80.99	97.15	97.83	97.86

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:

Test kmac_entropy_refresh has 1 failures.

11.kmac_entropy_refresh.18488072678257100811122812066555751101488363821492177957447401352211512287161
Line 186, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

  UVM_ERROR @ 25838940750 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 25838940750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

18.kmac_stress_all.105498660374616300559749271781092775836241058350003560686462287437376148728563
Line 147, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_ERROR @ 6766542504 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 6766542504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

32.kmac_smoke.85287118987434903696575595185990388854536391652774780978924822060188637262985
Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/32.kmac_smoke/latest/run.log

  UVM_ERROR @  41517641 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  41517641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:525) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 1.kmac_stress_all_with_rand_reset.40206069071496424986789057624589573743707472584007607154412093896054996941602
    Line 353, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3776424251 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 3776424251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.kmac_stress_all_with_rand_reset.104584401515133212347899288738192124608574068097535827401191803411697516988009
    Line 191, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1401600035 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 1401600035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```