KMAC/UNMASKED Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	56.600s	5.731ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.450s	36.777us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.510s	101.910us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.430s	1.617ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.250s	2.113ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.080s	42.804us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.510s	101.910us	20	20	100.00
		kmac_csr_aliasing	7.250s	2.113ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.070s	29.950us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.850s	37.294us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.573m	546.063ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.629m	43.548ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.608m	106.240ms	5	5	100.00
		kmac_test_vectors_sha3_256	32.782m	619.448ms	5	5	100.00
		kmac_test_vectors_sha3_384	22.829m	630.752ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.962m	49.970ms	5	5	100.00
		kmac_test_vectors_shake_128	24.166m	19.924ms	5	5	100.00
		kmac_test_vectors_shake_256	20.894m	24.750ms	5	5	100.00
		kmac_test_vectors_kmac	2.520s	108.840us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.690s	174.563us	5	5	100.00
V2	sideload	kmac_sideload	6.776m	21.204ms	50	50	100.00
V2	app	kmac_app	5.420m	13.033ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.196m	45.629ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.211m	46.286ms	50	50	100.00
V2	error	kmac_error	6.511m	56.801ms	50	50	100.00
V2	key_error	kmac_key_error	12.750s	7.228ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	2.158m	10.009ms	41	50	82.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.710s	1.050ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.420s	1.952ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	55.990s	10.220ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.680s	3.363ms	50	50	100.00
V2	stress_all	kmac_stress_all	34.284m	377.239ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.210s	69.476us	50	50	100.00
V2	alert_test	kmac_alert_test	1.200s	111.136us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.150s	136.928us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.150s	136.928us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.450s	36.777us	5	5	100.00
		kmac_csr_rw	1.510s	101.910us	20	20	100.00
		kmac_csr_aliasing	7.250s	2.113ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	324.637us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.450s	36.777us	5	5	100.00
		kmac_csr_rw	1.510s	101.910us	20	20	100.00
		kmac_csr_aliasing	7.250s	2.113ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	324.637us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.670s	87.129us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.670s	87.129us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.670s	87.129us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.670s	87.129us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.450s	1.265ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.305m	28.641ms	5	5	100.00
		kmac_tl_intg_err	5.270s	757.912us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.270s	757.912us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.680s	3.363ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	56.600s	5.731ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.776m	21.204ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.670s	87.129us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.305m	28.641ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.305m	28.641ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.305m	28.641ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	56.600s	5.731ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.680s	3.363ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.305m	28.641ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.737m	74.597ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	56.600s	5.731ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.398m	23.736ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			926	940	98.51

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.47	97.69	94.52	100.00	71.90	96.04	97.74	96.40

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:

  • Test kmac_sideload_invalid has 3 failures.

    • 2.kmac_sideload_invalid.106514505843084806297865681215322936536250799604090313416010888400095359339208
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10009339601 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x19ebf000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10009339601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.kmac_sideload_invalid.62644986439593897409186850656526254623340136157838008995249904515107964621931
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10017430296 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xea82000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10017430296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 1.kmac_stress_all_with_rand_reset.24673877930685410023008218806142848270010210115545377812142776235210900626873
      Line 158, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2835248581 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2835248581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.kmac_stress_all_with_rand_reset.30709633574880508960408898766246012596565496814248183730209547067628808210023
      Line 92, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4014332580 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4014332580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:525) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 3.kmac_stress_all_with_rand_reset.308334420707631908725935037629572105578820477772048004409944511217949645579
      Line 246, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2391506288 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 2391506288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.kmac_stress_all_with_rand_reset.64305636737637953093293672277669070581274822277191047098897111104097088912993
      Line 221, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13125725749 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 13125725749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 25.kmac_sideload_invalid.22768942552031006202547458867482420986835567524038776377128564361565355199699
      Line 87, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10094240533 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfcdef000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
        UVM_INFO @ 10094240533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 29.kmac_sideload_invalid.73295843385993139484998527868376002013883833785250665533022129952470256393444
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10283454080 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x99316000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
        UVM_INFO @ 10283454080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 35.kmac_sideload_invalid.10593004756359248217112494731316220190391351801065875281971153265677694894462
      Line 85, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10169534942 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x44a5d000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
        UVM_INFO @ 10169534942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 41.kmac_sideload_invalid.57632303201531059540123336585789886226713087159024596056885964050025943440257
      Line 89, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 11035257999 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xccbce000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
        UVM_INFO @ 11035257999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 42.kmac_sideload_invalid.110402281719563787383374790289322446182011461645044831539495373555254821227558
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10091054786 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x97465000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10091054786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 44.kmac_sideload_invalid.77564229538906741764825666046511477681127580815008448651977022312119848429317
      Line 88, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10106149540 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6a626000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
        UVM_INFO @ 10106149540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 47.kmac_key_error.70549546533800793922239920730096961588348209914642858266376587632647130353215
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/47.kmac_key_error/latest/run.log

        UVM_ERROR @ 987787970 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 987787970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---