OTBN Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 14.000s 47.827us 0 1 0.00
V1 single_binary otbn_single 15.667m 2.807ms 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 75.202us 5 5 100.00
V1 csr_rw otbn_csr_rw 7.000s 27.813us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 38.657us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 5.000s 143.337us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 13.000s 37.963us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 7.000s 27.813us 20 20 100.00
otbn_csr_aliasing 5.000s 143.337us 5 5 100.00
V1 mem_walk otbn_mem_walk 43.000s 1.786ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 22.000s 1.713ms 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 1.467m 348.507us 0 10 0.00
V2 multi_error otbn_multi_err 58.000s 392.209us 0 1 0.00
V2 back_to_back otbn_multi 1.917m 875.631us 0 10 0.00
V2 stress_all otbn_stress_all 1.683m 387.740us 0 10 0.00
V2 lc_escalation otbn_escalate 44.000s 198.801us 23 60 38.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 11.000s 20.699us 1 5 20.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 21.000s 72.738us 0 10 0.00
V2 alert_test otbn_alert_test 11.000s 19.768us 50 50 100.00
V2 intr_test otbn_intr_test 7.000s 23.592us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 11.000s 1.071ms 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 11.000s 1.071ms 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 75.202us 5 5 100.00
otbn_csr_rw 7.000s 27.813us 20 20 100.00
otbn_csr_aliasing 5.000s 143.337us 5 5 100.00
otbn_same_csr_outstanding 6.000s 30.475us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 75.202us 5 5 100.00
otbn_csr_rw 7.000s 27.813us 20 20 100.00
otbn_csr_aliasing 5.000s 143.337us 5 5 100.00
otbn_same_csr_outstanding 6.000s 30.475us 20 20 100.00
V2 TOTAL 164 246 66.67
V2S mem_integrity otbn_imem_err 14.000s 39.170us 0 10 0.00
otbn_dmem_err 29.000s 178.023us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 1.750m 403.833us 0 5 0.00
otbn_controller_ispr_rdata_err 11.000s 53.677us 0 5 0.00
otbn_mac_bignum_acc_err 13.000s 29.059us 0 5 0.00
otbn_urnd_err 12.000s 75.135us 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 9.000s 33.023us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 195.223us 1 2 50.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 10.000s 71.568us 7 10 70.00
V2S tl_intg_err otbn_sec_cm 2.683m 1.433ms 3 5 60.00
otbn_tl_intg_err 1.700m 630.862us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 26.000s 346.976us 18 20 90.00
V2S prim_fsm_check otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 14.000s 47.827us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 29.000s 178.023us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 14.000s 39.170us 0 10 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 1.700m 630.862us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 44.000s 198.801us 23 60 38.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 14.000s 39.170us 0 10 0.00
otbn_dmem_err 29.000s 178.023us 0 15 0.00
otbn_zero_state_err_urnd 11.000s 20.699us 1 5 20.00
otbn_illegal_mem_acc 9.000s 33.023us 5 5 100.00
otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 14.000s 39.170us 0 10 0.00
otbn_dmem_err 29.000s 178.023us 0 15 0.00
otbn_zero_state_err_urnd 11.000s 20.699us 1 5 20.00
otbn_illegal_mem_acc 9.000s 33.023us 5 5 100.00
otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 44.000s 198.801us 23 60 38.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 14.000s 39.170us 0 10 0.00
otbn_dmem_err 29.000s 178.023us 0 15 0.00
otbn_zero_state_err_urnd 11.000s 20.699us 1 5 20.00
otbn_illegal_mem_acc 9.000s 33.023us 5 5 100.00
otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 14.000s 39.579us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 17.000s 57.638us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 37.000s 456.503us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 37.000s 456.503us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 13.000s 29.803us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 32.000s 107.053us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 11.000s 22.805us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 11.000s 22.805us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 20.000s 111.047us 2 7 28.57
V2S sec_cm_data_mem_sec_wipe otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.917m 875.631us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 36.000s 252.683us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 15.667m 2.807ms 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 2.683m 1.433ms 3 5 60.00
V2S TOTAL 61 163 37.42
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.067m 3.411ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 290 585 49.57

Failure Buckets