ROM_CTRL/32KB Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.350s	177.984us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.650s	297.465us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.730s	730.755us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.930s	1.073ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.470s	541.517us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.510s	178.607us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.730s	730.755us	20	20	100.00
		rom_ctrl_csr_aliasing	6.470s	541.517us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.450s	866.144us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.840s	172.993us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	4.420s	228.327us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	28.610s	1.096ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.470s	1.085ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	6.700s	178.522us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.570s	197.689us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.570s	197.689us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.650s	297.465us	5	5	100.00
		rom_ctrl_csr_rw	7.730s	730.755us	20	20	100.00
		rom_ctrl_csr_aliasing	6.470s	541.517us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.400s	320.478us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.650s	297.465us	5	5	100.00
		rom_ctrl_csr_rw	7.730s	730.755us	20	20	100.00
		rom_ctrl_csr_aliasing	6.470s	541.517us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.400s	320.478us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	33.410s	7.097ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.421m	1.016ms	2	5	40.00
		rom_ctrl_tl_intg_err	1.266m	435.901us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.421m	1.016ms	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.421m	1.016ms	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.421m	1.016ms	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.421m	1.016ms	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.350s	177.984us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.350s	177.984us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.350s	177.984us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.266m	435.901us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
		rom_ctrl_kmac_err_chk	7.470s	1.085ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.943m	14.601ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	33.410s	7.097ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.421m	1.016ms	2	5	40.00
V2S		TOTAL			59	65	90.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	10.935m	5.507ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			260	266	97.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.
  - 2.rom_ctrl_corrupt_sig_fatal_chk.86786285996586306037025905048697179010120822274993461593484172602195861225858
    Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1890710858 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1890710858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.rom_ctrl_corrupt_sig_fatal_chk.84693060123139179213695524261804443686019414036651871190980865731925924066616
    Line 103, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1035728296 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1035728296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

0.rom_ctrl_sec_cm.35025949227026107268526650146334675997242416222637699784179215736145424578132
Line 175, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 23376012ps failed at 23376012ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 23376012ps failed at 23376012ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

2.rom_ctrl_sec_cm.48978051773933394922689116686089323972410429315505201944625331502094431068439
Line 220, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 10497711ps failed at 10497711ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 10497711ps failed at 10497711ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

1.rom_ctrl_sec_cm.68436511178854533516623244847448696396183337707524997762754363390254075368563
Line 302, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 215289097ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 215289097ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
  Starting assertion attempts at time 215289097ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))