ROM_CTRL/64KB Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.580s	1.122ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.540s	378.400us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	11.730s	291.776us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.390s	1.454ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.640s	10.943ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	10.730s	613.387us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	11.730s	291.776us	20	20	100.00
		rom_ctrl_csr_aliasing	15.640s	10.943ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.540s	290.652us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.510s	2.287ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.390s	393.824us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	1.205m	15.833ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	17.180s	560.949us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	16.610s	4.148ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.550s	302.131us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.550s	302.131us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.540s	378.400us	5	5	100.00
		rom_ctrl_csr_rw	11.730s	291.776us	20	20	100.00
		rom_ctrl_csr_aliasing	15.640s	10.943ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.860s	309.300us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.540s	378.400us	5	5	100.00
		rom_ctrl_csr_rw	11.730s	291.776us	20	20	100.00
		rom_ctrl_csr_aliasing	15.640s	10.943ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.860s	309.300us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	54.920s	1.597ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.148m	664.770us	0	5	0.00
		rom_ctrl_tl_intg_err	1.848m	475.623us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.148m	664.770us	0	5	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.148m	664.770us	0	5	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.148m	664.770us	0	5	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.148m	664.770us	0	5	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.580s	1.122ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.580s	1.122ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.580s	1.122ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.848m	475.623us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
		rom_ctrl_kmac_err_chk	17.180s	560.949us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.663m	7.865ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	54.920s	1.597ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.148m	664.770us	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.924m	15.645ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 3 failures:

  • Test rom_ctrl_sec_cm has 3 failures.

    • 2.rom_ctrl_sec_cm.57892223761074796163881955240068361667346365001203178347171955391075171910000
      Line 174, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 74306234ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 74306234ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 74306234ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • 3.rom_ctrl_sec_cm.69535376810732749118259984579388203324650661318880795540026910140290497098531
      Line 300, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 50802381ps failed at 50802381ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 50802381ps failed at 50802381ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

    • ... and 1 more failures.

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.28539725191169445755296672243801672790985932300127657311234586996984344435068
      Line 161, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9523677ps failed at 9523677ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 9563677ps failed at 9563677ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 1.rom_ctrl_sec_cm.108869421401837282601488623665192364147690175609661334871011112467312234300764
      Line 177, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 77094395ps failed at 77094395ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 77094395ps failed at 77094395ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'