RV_TIMER Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.870s	46.298us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.830s	12.413us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.840s	13.278us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.900s	854.677us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.100s	117.373us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.430s	29.399us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.840s	13.278us	20	20	100.00
		rv_timer_csr_aliasing	1.100s	117.373us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	17.130s	28.058ms	20	20	100.00
V2	disabled	rv_timer_disabled	4.070s	1.864ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.574m	552.068ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.574m	552.068ms	10	10	100.00
V2	stress	rv_timer_stress_all	6.690s	3.653ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.850s	33.566us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.840s	14.186us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.470s	794.755us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.470s	794.755us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.830s	12.413us	5	5	100.00
		rv_timer_csr_rw	0.840s	13.278us	20	20	100.00
		rv_timer_csr_aliasing	1.100s	117.373us	5	5	100.00
		rv_timer_same_csr_outstanding	0.960s	187.930us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.830s	12.413us	5	5	100.00
		rv_timer_csr_rw	0.840s	13.278us	20	20	100.00
		rv_timer_csr_aliasing	1.100s	117.373us	5	5	100.00
		rv_timer_same_csr_outstanding	0.960s	187.930us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.230s	1.332ms	5	5	100.00
		rv_timer_tl_intg_err	1.970s	857.164us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.970s	857.164us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	0.850s	17.665us	10	10	100.00
V3	max_value	rv_timer_max	0.800s	12.344us	10	10	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	52.980s	6.349ms	20	20	100.00
V3		TOTAL			40	40	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.91	100.00	100.00	78.66	--	100.00	96.82	100.00