SPI_DEVICE/1R1W Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.201m	72.205ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.710s	40.307us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.040s	491.561us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.300s	12.066ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.830s	3.682ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.620s	159.595us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.040s	491.561us	20	20	100.00
		spi_device_csr_aliasing	17.830s	3.682ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.030s	13.966us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.310s	48.149us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.140s	20.471us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.080s	8.666us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.910s	25.512us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.750s	634.240us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.750s	634.240us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	37.290s	9.769ms	50	50	100.00
		spi_device_tpm_sts_read	1.360s	163.992us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	41.390s	8.681ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	18.990s	31.389ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	45.860s	12.253ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	45.860s	12.253ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.540s	4.117ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.540s	4.117ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.540s	4.117ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.540s	4.117ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.540s	4.117ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	24.590s	7.853ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.163m	36.748ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.163m	36.748ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.163m	36.748ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	51.110s	4.454ms	50	50	100.00
		spi_device_read_buffer_direct	17.900s	3.900ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.163m	36.748ms	50	50	100.00
		spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.038m	62.012ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	19.530s	3.076ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	19.530s	3.076ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.201m	72.205ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.066m	345.797ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.702m	195.100ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.120s	16.746us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.090s	21.233us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.120s	720.837us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.120s	720.837us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.710s	40.307us	5	5	100.00
		spi_device_csr_rw	3.040s	491.561us	20	20	100.00
		spi_device_csr_aliasing	17.830s	3.682ms	5	5	100.00
		spi_device_same_csr_outstanding	3.910s	120.244us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.710s	40.307us	5	5	100.00
		spi_device_csr_rw	3.040s	491.561us	20	20	100.00
		spi_device_csr_aliasing	17.830s	3.682ms	5	5	100.00
		spi_device_same_csr_outstanding	3.910s	120.244us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	1.650s	412.248us	5	5	100.00
		spi_device_tl_intg_err	20.160s	3.944ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.160s	3.944ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.252m	74.576ms	50	50	100.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.11	96.58	71.19	89.36	98.42	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.81271847243657476157969813550055409077814244216207698065390854898369374454646
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1246672 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[59])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1246672 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1246672 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[955])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.32806838908841716788377062252604870239313320750340103817505656188466462792957
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1989990 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[38])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1989990 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1989990 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[934])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.102406522777319329756268349165994701185220760752022238731291571075398774878265
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @  22650195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf7f177 [111101111111000101110111] vs 0x0 [0])
        UVM_ERROR @  22725195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x546e65 [10101000110111001100101] vs 0x0 [0])
        UVM_ERROR @  22758195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdb27e1 [110110110010011111100001] vs 0x0 [0])
        UVM_ERROR @  22851195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8fb01e [100011111011000000011110] vs 0x0 [0])
        UVM_ERROR @  22926195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5c7563 [10111000111010101100011] vs 0x0 [0])
      

• UVM_ERROR (spi_device_scoreboard.sv:2236) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

  • Test spi_device_cfg_cmd has 1 failures.

    • 49.spi_device_cfg_cmd.18754107971843082551878711856016637211402083230239341950882376744086007357488
      Line 86, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest/run.log

        UVM_ERROR @ 2097890203 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x281a96) != exp '{'{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}, '{other_status:'h347dc3, wel:'h0, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}}
        UVM_ERROR @ 2098510203 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x281a96) != exp '{'{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}, '{other_status:'h347dc3, wel:'h0, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}}
        UVM_ERROR @ 2098680203 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x281a96) != exp '{'{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}, '{other_status:'h347dc3, wel:'h0, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}}
        UVM_ERROR @ 2098820203 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x281a96) != exp '{'{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}, '{other_status:'h347dc3, wel:'h0, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}}
        UVM_ERROR @ 2099240203 ps: (spi_device_scoreboard.sv:2236) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x281a96) != exp '{'{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'h2a0d0f, wel:'h1, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}, '{other_status:'ha06a5, wel:'h0, busy:'h0}, '{other_status:'h1ee751, wel:'h0, busy:'h0}}