SPI_HOST Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.767m	9.929ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	19.519us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	51.534us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	104.815us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	70.189us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	45.377us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	51.534us	20	20	100.00
		spi_host_csr_aliasing	3.000s	70.189us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	66.855us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	18.446us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	44.000s	54.441us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.033m	2.511ms	50	50	100.00
		spi_host_error_cmd	44.000s	18.553us	50	50	100.00
		spi_host_event	10.483m	16.515ms	50	50	100.00
V2	clock_rate	spi_host_speed	48.000s	958.938us	49	50	98.00
V2	speed	spi_host_speed	48.000s	958.938us	49	50	98.00
V2	chip_select_timing	spi_host_speed	48.000s	958.938us	49	50	98.00
V2	sw_reset	spi_host_sw_reset	1.767m	4.976ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	44.000s	77.002us	50	50	100.00
V2	cpol_cpha	spi_host_speed	48.000s	958.938us	49	50	98.00
V2	full_cycle	spi_host_speed	48.000s	958.938us	49	50	98.00
V2	duplex	spi_host_smoke	1.767m	9.929ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.767m	9.929ms	50	50	100.00
V2	stress_all	spi_host_stress_all	37.800m	1.000s	49	50	98.00
V2	spien	spi_host_spien	4.250m	54.379ms	50	50	100.00
V2	stall	spi_host_status_stall	7.467m	10.758ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	44.000s	50.229us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.033m	2.511ms	50	50	100.00
V2	alert_test	spi_host_alert_test	44.000s	21.490us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	27.624us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	156.992us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	156.992us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	19.519us	5	5	100.00
		spi_host_csr_rw	3.000s	51.534us	20	20	100.00
		spi_host_csr_aliasing	3.000s	70.189us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	60.842us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	19.519us	5	5	100.00
		spi_host_csr_rw	3.000s	51.534us	20	20	100.00
		spi_host_csr_aliasing	3.000s	70.189us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	60.842us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	96.830us	20	20	100.00
		spi_host_sec_cm	44.000s	72.498us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	96.830us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	15.217m	38.739ms	10	10	100.00
		TOTAL			838	840	99.76

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 26.spi_host_speed.50399832120642302662310396517764235388632472988370588661257471458835964162338
      Line 272, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/26.spi_host_speed/latest/run.log

        UVM_FATAL @ 10023311669 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x4efeb14, Comparison=CompareOpEq, exp_data=0x0, call_count=48
        UVM_INFO @ 10023311669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_stress_all has 1 failures.

    • 41.spi_host_stress_all.69772408701074712152672803148761666273652601408309412136850525083836826416032
      Line 340, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/41.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test spi_host has 1 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/spi_host-sim-xcelium/cov_merge/merged/cov_merge.log

        [Executing]:
        make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
      
        [make]: cov_merge
        imc -64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl
        *I,imc.tool.cov.version.diff: "There is a difference between the IMC tool version 22.09 and the coverage version 21.09-s006"
        Error: Cannot invoke "jdk.internal.platform.CgroupInfo.getMountPoint()" because "<parameter1>" is null
        Created log file /nightly/current_run/opentitan/startup.log
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
      

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test spi_host has 1 failures.
    • cov_report
      Log /nightly/current_run/scratch/master/spi_host-sim-xcelium/cov_report/cov_report.log