SRAM_CTRL/MAIN Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.883m	2.629ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.010s	136.439us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	15.612us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.490s	116.200us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.090s	16.709us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.510s	1.444ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	15.612us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	16.709us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.069m	25.626ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.757m	8.751ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	20.103m	147.987ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.179m	91.987ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	40.076m	179.610ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.120m	41.495ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.004m	55.474ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.757m	113.416ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.904m	872.307us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.661m	26.199ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.753m	3.052ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.902m	1.601ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.949m	3.655ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.102m	5.237ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.990s	6.679ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.817h	5.583s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.040s	29.762us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.660s	143.832us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.660s	143.832us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.010s	136.439us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	15.612us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	16.709us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.080s	26.035us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.010s	136.439us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	15.612us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	16.709us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.080s	26.035us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.061m	7.058ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.980s	18.002us	0	5	0.00
		sram_ctrl_tl_intg_err	3.780s	860.371us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.980s	18.002us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.780s	860.371us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.102m	5.237ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	28.102m	5.237ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	15.612us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.757m	113.416ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.757m	113.416ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.757m	113.416ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.004m	55.474ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	13.110s	11.058ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.061m	7.058ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.960s	5.537ms	33	50	66.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.883m	2.629ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.883m	2.629ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.757m	113.416ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.980s	18.002us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.004m	55.474ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.980s	18.002us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.980s	18.002us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.883m	2.629ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.980s	18.002us	0	5	0.00
V2S		TOTAL			116	145	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.692m	3.580ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1161	1190	97.56

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 17 failures:

  • Test sram_ctrl_readback_err has 17 failures.

    • 12.sram_ctrl_readback_err.1092965647414710368384792581811809868515626071804668338106880994709927949796
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 4694556836 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x10)
        UVM_INFO @ 4694556836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.sram_ctrl_readback_err.41261197256607034827413653093533173599484962718552878439065411437152942342523
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/14.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 676760410 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6b) != exp (0x4c)
        UVM_INFO @ 676760410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 15 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:

  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 0.sram_ctrl_mubi_enc_err.43486555207075330742029620224277819081113536312901885754882859995964431838001
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 5093612311 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 5093612311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_mubi_enc_err.67530844866474516686780442288512171572960949952638902193074798133907732859278
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 657575490 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 657575490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.89982113835877264366288881060679601092342238399829502919484144893564891443911
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4350201 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4350201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.101392939429206389882268993313678742686304049931219047530564604226765629886251
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  18001901 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  18001901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.49320072450047844444585987880835346041641307976463341417904330449004369063963
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4950988 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4950988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.39703312071593378040116452978883562383587610377905172628935912335660734291038
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @  36227689 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  36227689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---