SRAM_CTRL/RET Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: e14e4d4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.581m	147.622us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.020s	22.701us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.010s	13.953us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.370s	670.573us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.980s	52.807us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.630s	10.006ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.010s	13.953us	20	20	100.00
		sram_ctrl_csr_aliasing	0.980s	52.807us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.680s	605.927us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.810s	244.618us	49	50	98.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	18.456m	24.863ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.657m	14.244ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.601m	51.549ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.346m	24.556ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.890s	939.323us	50	50	100.00
V2	executable	sram_ctrl_executable	30.041m	49.411ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.747m	1.015ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.120m	261.118ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.778m	164.569us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.767m	727.695us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.709m	297.198us	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.583m	15.485ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.410s	112.490us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.385h	251.557ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.990s	17.162us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.800s	136.541us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.800s	136.541us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.020s	22.701us	5	5	100.00
		sram_ctrl_csr_rw	1.010s	13.953us	20	20	100.00
		sram_ctrl_csr_aliasing	0.980s	52.807us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.090s	26.075us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.020s	22.701us	5	5	100.00
		sram_ctrl_csr_rw	1.010s	13.953us	20	20	100.00
		sram_ctrl_csr_aliasing	0.980s	52.807us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.090s	26.075us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.560s	815.017us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.060s	36.210us	0	5	0.00
		sram_ctrl_tl_intg_err	2.980s	616.135us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.060s	36.210us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.980s	616.135us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.583m	15.485ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.583m	15.485ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.010s	13.953us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.041m	49.411ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.041m	49.411ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.041m	49.411ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.890s	939.323us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.520s	60.038us	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.560s	815.017us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.660s	106.539us	36	50	72.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.581m	147.622us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.581m	147.622us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.041m	49.411ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.060s	36.210us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.890s	939.323us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.060s	36.210us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.060s	36.210us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.581m	147.622us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.060s	36.210us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.224m	2.579ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			1160	1190	97.48

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.61	99.07	92.90	85.37	100.00	97.98	95.79	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 14 failures:

  • Test sram_ctrl_readback_err has 14 failures.

    • 4.sram_ctrl_readback_err.83284968754590529475913194120600790268335767096809187949185611852480257941944
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 104811825 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x58) != exp (0x2b)
        UVM_INFO @ 104811825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.28031219073372481340715314038496801650102800446180390458870455954775916772557
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23458340 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6b) != exp (0x29)
        UVM_INFO @  23458340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 12 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:

  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 8.sram_ctrl_mubi_enc_err.68874293186206624041649610968874322903239108378429180673982531363024775000017
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  23575244 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  23575244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_mubi_enc_err.85979359240365729567673634619831792672516296158955127570219544693048042072149
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 101037825 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 101037825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.112365011025024884564252566288090672603225101678858017629789350729299843929945
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1752304 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1752304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.62277190585641797894966049470610373083720857557428649328570831915321239253270
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  36210248 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  36210248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.22296899675610139446133610380158717365010445212713928101368408444100180447862
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1040842 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1040842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.56576836778854731564035384544585895070528023990905252085003338436944602513708
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @    921712 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @    921712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.sram_ctrl_stress_all_with_rand_reset.11877558271819852761640760157490464883311779898563918181944391760403497630289
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3338868466 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3338868466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 47.sram_ctrl_stress_all_with_rand_reset.62168922806050241608941331950046042014286698168405685019881636536714124627757
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 834005363 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 834005363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:849) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.sram_ctrl_stress_all_with_rand_reset.49591204815716547717321905591212617192662727008483126572589474411973307525069
      Line 103, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111164067 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 111164067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 14.sram_ctrl_csr_mem_rw_with_rand_reset.30289021600023797721787775245751389319427582186769059521817384393740386392758
      Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10006285467 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10006285467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:

  • Test sram_ctrl_mem_partial_access has 1 failures.

    • 26.sram_ctrl_mem_partial_access.35715032572454527455674961715964639318411673992749005359113327996678049227945
      Line 129, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest/run.log

            Offending '((pend_req[101].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
        UVM_ERROR @ 417017623 ps: (tlul_assert.sv:319) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
        UVM_INFO @ 417017623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---