UART Simulation Results

Friday September 12 2025 21:26:36 UTC

GitHub Revision: `e14e4d4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.020s	5.308ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.910s	17.031us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.910s	19.960us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.620s	1.029ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.990s	137.212us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.550s	454.677us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.910s	19.960us	20	20	100.00
		uart_csr_aliasing	0.990s	137.212us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.038m	134.416ms	50	50	100.00
V2	parity	uart_smoke	24.020s	5.308ms	50	50	100.00
		uart_tx_rx	3.038m	134.416ms	50	50	100.00
V2	parity_error	uart_intr	14.275m	594.851ms	50	50	100.00
		uart_rx_parity_err	12.393m	302.239ms	50	50	100.00
V2	watermark	uart_tx_rx	3.038m	134.416ms	50	50	100.00
		uart_intr	14.275m	594.851ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.456m	192.997ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.252m	230.954ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.041m	250.112ms	299	300	99.67
V2	rx_frame_err	uart_intr	14.275m	594.851ms	50	50	100.00
V2	rx_break_err	uart_intr	14.275m	594.851ms	50	50	100.00
V2	rx_timeout	uart_intr	14.275m	594.851ms	50	50	100.00
V2	perf	uart_perf	19.962m	25.279ms	50	50	100.00
V2	sys_loopback	uart_loopback	30.710s	15.284ms	50	50	100.00
V2	line_loopback	uart_loopback	30.710s	15.284ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.590m	80.658ms	11	50	22.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.797m	48.330ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.690s	6.711ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.081m	7.875ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.086m	119.848ms	50	50	100.00
V2	stress_all	uart_stress_all	17.957m	243.453ms	43	50	86.00
V2	alert_test	uart_alert_test	0.880s	42.295us	50	50	100.00
V2	intr_test	uart_intr_test	0.890s	12.750us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.960s	335.411us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.960s	335.411us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.910s	17.031us	5	5	100.00
		uart_csr_rw	0.910s	19.960us	20	20	100.00
		uart_csr_aliasing	0.990s	137.212us	5	5	100.00
		uart_same_csr_outstanding	1.100s	28.329us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.910s	17.031us	5	5	100.00
		uart_csr_rw	0.910s	19.960us	20	20	100.00
		uart_csr_aliasing	0.990s	137.212us	5	5	100.00
		uart_same_csr_outstanding	1.100s	28.329us	20	20	100.00
V2		TOTAL			1043	1090	95.69
V2S	tl_intg_err	uart_sec_cm	1.310s	1.062ms	5	5	100.00
		uart_tl_intg_err	1.690s	485.805us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.690s	485.805us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.453m	4.134ms	89	100	89.00
V3		TOTAL			89	100	89.00
		TOTAL			1262	1320	95.61

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	99.48	98.25	74.67	--	98.14	97.12	99.59

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 28 failures:

Test uart_noise_filter has 20 failures.

2.uart_noise_filter.104324783994895770140445226383829545973931842206591211487740558543496703335627
Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log

  UVM_ERROR @ 57379680004 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 57385965844 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 57391370714 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 57392727884 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 57536802194 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 6,                                 clk_pulses: 0

4.uart_noise_filter.84671782936676868256626229942844399848885848078768559486779897787285550655718
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log

  UVM_ERROR @ 872769705 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 872769705 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 924259705 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 924259705 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 955959705 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0

... and 18 more failures.

Test uart_stress_all has 3 failures.

4.uart_stress_all.17607207651661004921753645510788067765975037331268578209141187768171117619275
Line 85, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_stress_all/latest/run.log

  UVM_ERROR @ 26637201078 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 26640337473 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 26643382958 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 26643973873 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 26644564788 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

14.uart_stress_all.99750129333962314145342953361155379336548484662063955853125295675363029924905
Line 107, in log /nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all/latest/run.log

  UVM_ERROR @ 31887615699 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 31887615699 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 31986691786 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 32236262272 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 32282701258 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 5 failures.

47.uart_stress_all_with_rand_reset.80348029519679885491400293431183692661131654560974042605183944299494643034053
Line 83, in log /nightly/current_run/scratch/master/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2406884724 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 2406884724 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 2409884724 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/204
  UVM_INFO @ 2656695374 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/10

51.uart_stress_all_with_rand_reset.50638979676820782291400534997852111848386639942591518570333541062834033678202
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   9005100 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @   9640537 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  14286519 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  14369855 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  17828299 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 3 more failures.

UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 15 failures:

Test uart_noise_filter has 13 failures.

7.uart_noise_filter.86645405056652712421615126226362035028194089757678521429022822971707803839558
Line 78, in log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log

  UVM_ERROR @ 59738617118 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7,                                 clk_pulses: 0
  UVM_ERROR @ 59738658785 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 59738700452 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (208 [0xd0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 59874409871 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 8,                                 clk_pulses: 0
  UVM_ERROR @ 59874451538 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

11.uart_noise_filter.73621386593884831019148033868786815323961151055122568362210511246240946541180
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log

  UVM_ERROR @ 23227950501 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 11,                                 clk_pulses: 0
  UVM_ERROR @ 23227960501 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 23227970501 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (110 [0x6e] vs 239 [0xef]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 23227980501 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 23227990501 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (110 [0x6e] vs 178 [0xb2]) reg name: uart_reg_block.rdata

... and 11 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

14.uart_stress_all_with_rand_reset.11854469925502744360327987987739864450024335170358828330720995693373145548363
Line 147, in log /nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15109621643 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 15109688310 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 15109754977 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (11 [0xb] vs 191 [0xbf]) reg name: uart_reg_block.rdata
  UVM_INFO @ 15302555941 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/43
  UVM_INFO @ 15908025635 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/43

Test uart_stress_all has 1 failures.

30.uart_stress_all.12128545983301970573568084114394443020350326864701904383380842790988845874433
Line 94, in log /nightly/current_run/scratch/master/uart-sim-vcs/30.uart_stress_all/latest/run.log

  UVM_ERROR @ 18846749197 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 18846792675 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 18846966587 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (95 [0x5f] vs 119 [0x77]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 19070791331 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 19070834809 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 10 failures:

Test uart_noise_filter has 6 failures.

0.uart_noise_filter.108701476688407062820001031481957001767912052354890059241181763146987272057941
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

  UVM_ERROR @ 660737217 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 660737217 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 660737217 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 689317217 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0
  UVM_ERROR @ 689357217 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (43 [0x2b] vs 255 [0xff]) reg name: uart_reg_block.rdata

5.uart_noise_filter.28688125388337625974546171570250780547894453506953356237675784723134394238608
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log

  UVM_ERROR @ 478883702 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 478883702 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 478883702 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 643737962 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 19,                                 clk_pulses: 0
  UVM_ERROR @ 643826198 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (116 [0x74] vs 255 [0xff]) reg name: uart_reg_block.rdata

... and 4 more failures.

Test uart_stress_all has 3 failures.

6.uart_stress_all.20657083010471227996056393889133377692151086646237587102892335577154688786884
Line 121, in log /nightly/current_run/scratch/master/uart-sim-vcs/6.uart_stress_all/latest/run.log

  UVM_ERROR @ 230443161103 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 230443161103 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 230443161103 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 230453201103 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 8
  UVM_ERROR @ 230453221103 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

12.uart_stress_all.34058874030950319414921452095161061134997925268365268692887574080950716395597
Line 79, in log /nightly/current_run/scratch/master/uart-sim-vcs/12.uart_stress_all/latest/run.log

  UVM_ERROR @ 153498873 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 153498873 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 153498873 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 189040431 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 1
  UVM_ERROR @ 192657351 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (92 [0x5c] vs 255 [0xff]) reg name: uart_reg_block.rdata

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

62.uart_stress_all_with_rand_reset.38493071821158544212562529525052291776775445492842883361066151351997910639282
Line 207, in log /nightly/current_run/scratch/master/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13041895490 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 13041895490 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 13041895490 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 13069937381 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/172
  UVM_ERROR @ 13140062942 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0

UVM_ERROR (cip_base_vseq.sv:849) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

30.uart_stress_all_with_rand_reset.42557744262634894753603723542908214842563996581281647231999895893977803727667
Line 107, in log /nightly/current_run/scratch/master/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2224178911 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2224178911 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 2224338911 ps: (cip_base_vseq.sv:873) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 4/5

53.uart_stress_all_with_rand_reset.32303636076511272453668974319163422782116439923436693939674851737068747205284
Line 96, in log /nightly/current_run/scratch/master/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4381126765 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4381126765 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 4381626769 ps: (cip_base_vseq.sv:873) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 3/10

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

32.uart_stress_all_with_rand_reset.73184557328830512255218807935380195425360101252375720247747374045943634728041
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   1667092 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @  54376358 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @  54426358 ps: (cip_base_vseq.sv:873) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/5

Test uart_fifo_reset has 1 failures.

249.uart_fifo_reset.68589037089980031473359248917316665038404558639827855673944522862997590912176
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/249.uart_fifo_reset/latest/run.log

  UVM_ERROR @ 6039981249 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 8137066263 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
  UVM_INFO @ 12799011249 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8
  UVM_INFO @ 93237191249 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 5/8
  UVM_INFO @ 94861861249 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 6/8

UVM_ERROR (cip_base_vseq.sv:945) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

72.uart_stress_all_with_rand_reset.70109512394207222649637860562973495964254750590312244797190018504230723308881
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 390509799 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 390541632 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 390541632 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 390545513 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2