e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 1.000s | 83.936us | 1 | 1 | 100.00 |
| V1 | smoke | aes_smoke | 51.000s | 2 | 50 | 4.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 34.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 37.000s | 0 | 20 | 0.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 37.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 43.000s | 1 | 20 | 5.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 37.000s | 0 | 20 | 0.00 | |
| aes_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 4 | 106 | 3.77 | |||
| V2 | algorithm | aes_smoke | 51.000s | 2 | 50 | 4.00 | |
| aes_config_error | 43.000s | 3 | 50 | 6.00 | |||
| aes_stress | 51.000s | 1 | 50 | 2.00 | |||
| V2 | key_length | aes_smoke | 51.000s | 2 | 50 | 4.00 | |
| aes_config_error | 43.000s | 3 | 50 | 6.00 | |||
| aes_stress | 51.000s | 1 | 50 | 2.00 | |||
| V2 | back2back | aes_stress | 51.000s | 1 | 50 | 2.00 | |
| aes_b2b | 47.000s | 6 | 50 | 12.00 | |||
| V2 | backpressure | aes_stress | 51.000s | 1 | 50 | 2.00 | |
| V2 | multi_message | aes_smoke | 51.000s | 2 | 50 | 4.00 | |
| aes_config_error | 43.000s | 3 | 50 | 6.00 | |||
| aes_stress | 51.000s | 1 | 50 | 2.00 | |||
| aes_alert_reset | 46.000s | 2 | 50 | 4.00 | |||
| V2 | failure_test | aes_man_cfg_err | 46.000s | 0 | 50 | 0.00 | |
| aes_config_error | 43.000s | 3 | 50 | 6.00 | |||
| aes_alert_reset | 46.000s | 2 | 50 | 4.00 | |||
| V2 | trigger_clear_test | aes_clear | 42.000s | 2 | 50 | 4.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 26.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 46.000s | 2 | 50 | 4.00 | |
| V2 | stress | aes_stress | 51.000s | 1 | 50 | 2.00 | |
| V2 | sideload | aes_stress | 51.000s | 1 | 50 | 2.00 | |
| aes_sideload | 47.000s | 2 | 50 | 4.00 | |||
| V2 | deinitialization | aes_deinit | 55.000s | 3 | 50 | 6.00 | |
| V2 | stress_all | aes_stress_all | 37.000s | 0 | 10 | 0.00 | |
| V2 | alert_test | aes_alert_test | 42.000s | 3 | 50 | 6.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 34.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 37.000s | 0 | 20 | 0.00 | |||
| aes_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 46.000s | 2 | 20 | 10.00 | |||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 34.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 37.000s | 0 | 20 | 0.00 | |||
| aes_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 46.000s | 2 | 20 | 10.00 | |||
| V2 | TOTAL | 24 | 501 | 4.79 | |||
| V2S | reseeding | aes_reseed | 46.000s | 2 | 50 | 4.00 | |
| V2S | fault_inject | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 47.000s | 4 | 20 | 20.00 | |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 47.000s | 4 | 20 | 20.00 | |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 47.000s | 4 | 20 | 20.00 | |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 47.000s | 4 | 20 | 20.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 42.000s | 3 | 20 | 15.00 | |
| V2S | tl_intg_err | aes_sec_cm | 34.000s | 0 | 5 | 0.00 | |
| aes_tl_intg_err | 46.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 46.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 46.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 47.000s | 4 | 20 | 20.00 | |
| V2S | sec_cm_main_config_sparse | aes_smoke | 51.000s | 2 | 50 | 4.00 | |
| aes_stress | 51.000s | 1 | 50 | 2.00 | |||
| aes_alert_reset | 46.000s | 2 | 50 | 4.00 | |||
| aes_core_fi | 50.000s | 3 | 70 | 4.29 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 47.000s | 4 | 20 | 20.00 | |
| V2S | sec_cm_aux_config_regwen | aes_readability | 46.000s | 2 | 50 | 4.00 | |
| aes_stress | 51.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 51.000s | 1 | 50 | 2.00 | |
| aes_sideload | 47.000s | 2 | 50 | 4.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 46.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 46.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 46.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 46.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 46.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 51.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_key_masking | aes_stress | 51.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_ctr_fi | 46.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 46.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_ctr_fi | 46.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 56.000s | 20 | 300 | 6.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| V2S | TOTAL | 51 | 985 | 5.18 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 46.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 79 | 1602 | 4.93 |
Job returned non-zero exit code has 1519 failures:
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.72443442516808156492274951911030389312408821595325345286111620327290450724187
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:21 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 47 failures.
0.aes_deinit.67282720412171206117307173300811430997845936029656375662553850113561164713859
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:16 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_deinit.73560771250934242979032172545218123923371300548674391588196116792467507260366
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:39 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
Test aes_man_cfg_err has 50 failures.
0.aes_man_cfg_err.45568946546803960894940506566745200346780566684015224794204523430179088660933
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:34 UTC (total: 00:00:39)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_man_cfg_err.92073085304759894997672024520563431504426671228989443659364126040885616071267
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:39 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 48 more failures.
Test aes_readability has 48 failures.
0.aes_readability.54504756582707979119373018662002481913171518653155368513439077120581692249946
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:34 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_readability.29451929354724512474895923855971517838383052945285834399303291698201032756844
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:37 UTC (total: 00:00:25)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
Test aes_smoke has 48 failures.
0.aes_smoke.9792801492436643354624779607102084896677086300792326537525830462961875416188
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:17 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_smoke.88147443273320388328465213725248075029490648591855956133262427147555223584428
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:35:51 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
... and 26 more tests.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 2 failures:
34.aes_cipher_fi.9953038172120003228778489260284823019117614026043145712070858292293727606427
Line 144, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/34.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10007477186 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007477186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
89.aes_cipher_fi.107161171431345719382328766432310215689153082388740535437541135802867023878959
Line 149, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/89.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10009851829 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009851829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
7.aes_stress_all_with_rand_reset.100299060658942253492646504440597725282278594406299083056326938011758172862608
Line 255, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1043266496 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1043266496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
44.aes_control_fi.56385619878356416170284967466832260979181552707898299326113508402302411759363
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/44.aes_control_fi/latest/run.log
Job timed out after 1 minutes
[Errno *] No such file or directory: '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.txt' has 1 failures:
cov_report
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.log
[Errno 2] No such file or directory: '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cov_report/cov_report.txt'