e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 55.000s | 3 | 50 | 6.00 | |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 47.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | csrng_csr_rw | 46.000s | 2 | 20 | 10.00 | |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | csrng_csr_aliasing | 43.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 47.000s | 2 | 20 | 10.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 46.000s | 2 | 20 | 10.00 | |
| csrng_csr_aliasing | 43.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 7 | 105 | 6.67 | |||
| V2 | interrupts | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| V2 | alerts | csrng_alert | 1.117m | 20 | 500 | 4.00 | |
| V2 | err | csrng_err | 55.000s | 20 | 500 | 4.00 | |
| V2 | cmds | csrng_cmds | 3.317m | 8.924ms | 2 | 50 | 4.00 |
| V2 | life cycle | csrng_cmds | 3.317m | 8.924ms | 2 | 50 | 4.00 |
| V2 | stress_all | csrng_stress_all | 9.233m | 40.708ms | 1 | 50 | 2.00 |
| V2 | intr_test | csrng_intr_test | 38.000s | 6 | 50 | 12.00 | |
| V2 | alert_test | csrng_alert_test | 43.000s | 4 | 50 | 8.00 | |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | csrng_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 47.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 46.000s | 2 | 20 | 10.00 | |||
| csrng_csr_aliasing | 43.000s | 0 | 5 | 0.00 | |||
| csrng_same_csr_outstanding | 47.000s | 1 | 20 | 5.00 | |||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 47.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 46.000s | 2 | 20 | 10.00 | |||
| csrng_csr_aliasing | 43.000s | 0 | 5 | 0.00 | |||
| csrng_same_csr_outstanding | 47.000s | 1 | 20 | 5.00 | |||
| V2 | TOTAL | 67 | 1440 | 4.65 | |||
| V2S | tl_intg_err | csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |
| csrng_tl_intg_err | 51.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_config_regwen | csrng_regwen | 46.000s | 4 | 50 | 8.00 | |
| csrng_csr_rw | 46.000s | 2 | 20 | 10.00 | |||
| V2S | sec_cm_config_mubi | csrng_alert | 1.117m | 20 | 500 | 4.00 | |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 9.233m | 40.708ms | 1 | 50 | 2.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 1.117m | 20 | 500 | 4.00 | |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 9.233m | 40.708ms | 1 | 50 | 2.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 1.117m | 20 | 500 | 4.00 | |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 51.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| csrng_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 46.000s | 13 | 200 | 6.50 | |
| csrng_err | 55.000s | 20 | 500 | 4.00 | |||
| V2S | TOTAL | 5 | 75 | 6.67 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 46.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 79 | 1630 | 4.85 |
Job returned non-zero exit code has 1549 failures:
0.csrng_smoke.107783100938372459698434041200331079206820242457955140200432440843178954415857
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:30 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_smoke.57044586880696563875409982580071000816067265230972525686440292516932776685390
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:24 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.csrng_stress_all.32097530587755402903204820642886938335639254477035451175676747286023814466741
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:32 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_stress_all.62343090586193943305780506026586846912072794403304548031431627053977544063252
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:29 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
0.csrng_intr.27056974405123930560608392928029327596929446773859450423611936572957196526685
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:33 UTC (total: 00:00:31)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_intr.43763822576325627139488350062711239217092079192897788044033897110124603900676
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:42 UTC (total: 00:00:33)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 183 more failures.
0.csrng_alert.41128708418975148549023226939355012697751095188972943956929070825071955003378
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:45 UTC (total: 00:00:42)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_alert.67681027129028725163115714737841736119026800694840457857012865059652087676798
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:35 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 478 more failures.
0.csrng_err.43342250057644839357534366986221906357236502095131624993041127827888333228639
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:24 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_err.25153079749047161362301348559141444898007648137186268556666848562279554432789
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 20, 2025 at 02:52:53 UTC (total: 00:00:43)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 478 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,515): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:
140.csrng_intr.20326033050093700902102200009430900165372543218751454162558877128241676790195
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/140.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,515): (time 56910422 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 56910422 ps: (csrng_cmd_stage.sv:515) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 56910422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 1 failures:
185.csrng_intr.59409856782381764700846992301430029619102259938861375897208876499052272610044
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/185.csrng_intr/latest/run.log
UVM_FATAL @ 206560025 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
----| PATH NOT FOUND
UVM_INFO @ 206560025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
[Errno *] No such file or directory: '/nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.txt' has 1 failures:
cov_report
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.log
[Errno 2] No such file or directory: '/nightly/current_run/scratch/master/csrng-sim-xcelium/cov_report/cov_report.txt'